AD5327 Просмотр технического описания (PDF) - Analog Devices
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AD5327 Datasheet PDF : 24 Pages
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AD5307/AD5317/AD5327
AC CHARACTERISTICS1 (VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless
otherwise noted.)
Parameter2
A, B Versions3
Min Typ Max
Unit
Conditions/Comments
Output Voltage Settling Time
AD5307
AD5317
AD5327
Slew Rate
Major-Code Change Glitch Energy
Digital Feedthrough
SDO Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
6
8
7
9
8
10
0.7
12
0.5
4
0.5
1
3
200
–70
NOTES
1Guaranteed by design and characterization; not production tested.
2See the Terminology section.
3Temperature range (A, B Versions): –40∞C to +105∞C; typical at +25∞C.
Specifications subject to change without notice.
ms
ms
ms
V/ms
nV-s
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
VREF = VDD = 5 V
1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
1/4 Scale to 3/4 Scale Change (0x100 to 0x300)
1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)
1 LSB Change around Major Carry
Daisy-Chain Mode; SDO Load is 10 pF
VREF = 2 V ± 0.1 V p-p. Unbuffered Mode
VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz
TIMING CHARACTERISTICS1, 2, 3
(VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.)
Parameter
A, B Versions
Limit at TMIN, TMAX
Unit
Conditions/Comments
t1
33
t2
13
t3
13
t4
13
t5
5
t6
4.5
t7
0
t8
50
t9
20
t10
20
t11
20
t12
0
t134, 5
20
25
t145
5
t155
8
t165
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
LDAC Pulsewidth
SCLK Falling Edge to LDAC Rising Edge
CLR Pulsewidth
SCLK Falling Edge to LDAC Falling Edge
SCLK Rising Edge to SDO Valid (VDD = 3.6 V to 5.5 V)
SCLK Rising Edge to SDO Valid (VDD = 2.5 V to 3.5 V)
SCLK Falling Edge to SYNC Rising Edge
SYNC Rising Edge to SCLK Rising Edge
SYNC Rising Edge to LDAC Falling Edge
NOTES
1Guaranteed by design and characterization; not production tested.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (VIL + VIH)/2.
3See Figures 2 and 3.
4This is measured with the load circuit of Figure 1. t13 determines maximum SCLK frequency in Daisy-Chain mode.
5Daisy-chain mode only.
Specifications subject to change without notice.
–4–
REV. A
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