AD5327 Просмотр технического описания (PDF) - Analog Devices

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Компоненты Описание

производитель

AD5327

2.5 V to 5.5 V, 400
A, Quad Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP

Analog Devices 

AD5307/AD5317/AD5327

Parameter1

A Version2

B Version2

Min Typ Max Min Typ Max Unit

Conditions/Comments

LOGIC INPUTS6

Input Current

VIL, Input Low Voltage

VIH, Input High Voltage

(Excluding DCEN)

1.7

VIH, Input High Voltage

(DCEN)

Pin Capacitance

LOGIC OUTPUT (SDO)6

VDD = 4.5 V to 5.5 V

Output Low Voltage, VOL

Output High Voltage, VOH

VDD = 2.5 V to 3.6 V

Output Low Voltage, VOL

Output High Voltage, VOH

Floating State Leakage Current

Floating State Output

Capacitance

2.4

2.1

2.0

3

VDD – 1

VDD – 0.5

3

±1

0.8

0.6

0.5

1.7

2.4

2.1

2.0

3

0.4

VDD – 1

0.4

VDD – 0.5

±1

3

±1 mA

0.8 V

0.6 V

0.5 V

V

V

V

V

pF

0.4 V

V

0.4 V

V

±1

mA

pF

VDD = 5 V ± 10%

VDD = 3 V ± 10%

VDD = 2.5 V

VDD = 2.5 V to 5.5 V; TTL and 1.8 V

CMOS Compatible

VDD = 5 V ± 10%

VDD = 3 V ± 10%

VDD = 2.5 V

ISINK = 2 mA

ISOURCE = 2 mA

ISINK = 2 mA

ISOURCE = 2 mA

DCEN = GND

DCEN = GND

POWER REQUIREMENTS

VDD

IDD (Normal Mode)8

VDD = 4.5 V to 5.5 V

VDD = 2.5 V to 3.6 V

IDD (Power-Down Mode)

VDD = 4.5 V to 5.5 V

VDD = 2.5 V to 3.6 V

2.5

5.5 2.5

5.5 V

500 900

500 900 mA

400 750

0.3 1

0.09 1

400 750 mA

0.3 1

mA

0.09 1

mA

VIH = VDD and VIL = GND

All DACs in Unbuffered Mode.

In Buffered Mode, extra current is

typically x mA per DAC

where x = 5 mA + VREF/RDAC.

VIH = VDD and VIL = GND

NOTES

1See the Terminology section.

2Temperature range (A, B Versions): –40∞C to +105∞C; typical at +25∞C.

3DC specifications tested with the outputs unloaded, unless stated otherwise.

4Linearity is tested using a reduced code range: AD5307 (Code 8 to 255); AD5317 (Code 28 to 1023); AD5327 (Code 115 to 4095).

5This corresponds to x codes. x = Deadband Voltage/LSB size.

6Guaranteed by design and characterization; not production tested.

7For the amplifier output to reach its minimum voltage, offset error must be negative; for the amplifier output to reach its maximum voltage, V REF = VDD and offset

plus gain error must be positive.

8Interface inactive. All DACs active. DAC outputs unloa-ded.

Specifications subject to change without notice.

REV. A

–3–

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