AD5317BRU-REEL Просмотр технического описания (PDF) - Analog Devices
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AD5317BRU-REEL
Analog Devices
AD5317BRU-REEL Datasheet PDF : 24 Pages
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2.5 V to 5.5 V, 400 A, Quad Voltage Output
8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5307/AD5317/AD5327*
FEATURES
AD5307: 4 Buffered 8-Bit DACs in 16-Lead TSSOP
A Version: ؎1 LSB INL, B Version: ؎0.625 LSB INL
AD5317: 4 Buffered 10-Bit DACs in 16-Lead TSSOP
A Version: ؎4 LSB INL, B Version: ؎2.5 LSB INL
AD5327: 4 Buffered 12-Bit DACs in 16-Lead TSSOP
A Version: ؎16 LSB INL, B Version: ؎10 LSB INL
Low Power Operation: 400 A @ 3 V, 500 A @ 5 V
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic by Design over All Codes
Power-Down to 90 nA @ 3 V, 300 nA @ 5 V (PD Pin)
Double-Buffered Input Logic
Buffered/Unbuffered Reference Input Options
Output Range: 0 V to VREF or 0 V to 2 VREF
Power-On Reset to 0 V
Simultaneous Update of Outputs (LDAC Pin)
Asynchronous Clear Facility (CLR Pin)
Low Power, SPI®, QSPI™, MICROWIRE™, and DSP
Compatible 3-Wire Serial Interface
SDO Daisy-Chaining Option
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range –40؇C to +105؇C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5307/AD5317/AD5327 are quad 8-, 10-, and 12-bit
buffered voltage-output DACs in a 16-lead TSSOP package that
operate from a single 2.5 V to 5.5 V supply, consuming 400 mA
at 3 V. Their on-chip output amplifiers allow the outputs to
swing rail-to-rail with a slew rate of 0.7 V/ms. The AD5307/
AD5317/AD5327 utilize a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI, QSPI, MICROWIRE, and DSP interface standards.
The references for the four DACs are derived from two refer-
ence pins (one per DAC pair). These reference inputs can be
configured as buffered or unbuffered inputs. The parts incorpo-
rate a power-on reset circuit, which ensures that the DAC outputs
power up to 0 V and remain there until a valid write to the device
takes place. There is also an asynchronous active low CLR pin
that clears all DACs to 0 V. The outputs of all DACs may be
updated simultaneously using the asynchronous LDAC input.
The parts contain a power-down feature that reduces the cur-
rent consumption of the devices to 300 nA @ 5 V (90 nA @
3 V). The parts may also be used in daisy-chaining applications
using the SDO pin.
All three parts are offered in the same pinout, which allows users
to select the amount of resolution appropriate for their applica-
tion without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFAB
AD5307/AD5317/AD5327
LDAC
INPUT
DAC
REGISTER REGISTER
STRING
DAC A
GAIN-SELECT
LOGIC
BUFFER
VOUTA
SCLK
SYNC
DIN
INTERFACE
LOGIC
INPUT
DAC
REGISTER REGISTER
STRING
DAC B
BUFFER
INPUT
DAC
REGISTER REGISTER
STRING
DAC C
BUFFER
VOUTB
VOUTC
SDO
INPUT
DAC
STRING
REGISTER REGISTER DAC D
BUFFER
VOUTD
POWER-ON
RESET
POWER-DOWN
LOGIC
DCEN LDAC CLR
*Protected by U.S. Patent No. 5,969,657; other patents pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
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