AD1882 Просмотр технического описания (PDF) - Analog Devices
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AD1882 Datasheet PDF : 16 Pages
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AD1882
Table 6. AD1882 Pin Descriptions
Mnemonic
Pin No. Function
Description
DIGITAL INTERFACE
SDATA_OUT
5
I
Link Serial Data Output. AD1882 input stream. Clocked on both edges of the
BIT_CLK.
BIT_CLK
6
I
Link Bit Clock. 24.000 MHz serial data clock.
SDATA_IN
8
I/O
Link Serial Data Input. AD1882 output stream Clocked only on one edge of BIT_CLK.
SYNC
10
I
Link Frame Sync.
RESET
11
I
Link Reset. AD1882 master hardware reset
DIGITAL I/O
GPIO_0
2
I/O
General-Purpose Input/Output Pin. Digital signal used to control external circuitry.
GPIO_1/EAPD
47
SPDIF_OUT
48
JACK SENSE AND EAPD
SENSE_A/SRC_B
13
SENSE_B/SRC_A
34
E ANALOG I/O
PCBEEP
12
PORT-E_L
14
T PORT-E_R
15
PORT-F_L
16
PORT-F_R
17
CD_L
18
E CD_GND
19
CD_R
20
PORT-B_L
21
L PORT-B_R
22
PORT-C_L
23
PORT-C_R
24
PORT-D_L
35
O PORT-D_R
36
PORT-A_L
39
MONO_OUT
40
PORT-A_R
41
S PORT-G_L
43
PORT-G_R
44
FILTER/REFERENCE
MIC_BIAS-B
28
MIC_BIAS-C
29
B MIC_BIAS-E
31
O DVCORE
1
I/O
General-Purpose Input/Output Pin/EAPD Pin. Digital signal used to control external
circuitry. Defaults to high-Z. When used as EAPD: high-Z = amp-on, DVSS = amp off.
O
S/PDIF_OUT. Supports S/PDIF output.
I/O
JACK SENSE A-D Input/Sense B Drive.
I/O
JACK SENSE E-H Input/Sense A Drive.
LI
LI, MIC, LO, SWAP
LI, MIC, LO, SWAP
I/O
I/O
LI
LI
LI
LI, MIC, HP, LO
LI, MIC, HP, LO
LI, MIC, LO
LI, MIC, LO
LI, HP, LO
LI, HP, LO
LI, MIC, HP, LO
LO
LI, MIC, HP, LO
LO, SWAP
LO, SWAP
Monaural Input from System for Analog PCBeep.
Auxiliary Input/Output Left Channel.
Auxiliary Input/Output Right Channel.
Auxiliary Input/Output Left Channel.
Auxiliary Input/Output Right Channel.
CD Audio Left Channel.
CD Audio Analog Ground Reference (for Differential CD Input). Must be connected to
AGND via 0.1 mF capacitor if not in use as CD_GND.
CD Audio Right Channel.
Front Panel Stereo MIC/Line-In.
Front Panel Stereo MIC/Line-In.
Rear Panel Stereo MIC/Line-In.
Rear Panel Stereo MIC/Line-In.
Rear Panel Headphone/Line-Out.
Rear Panel Headphone/Line-Out.
Front Panel Headphone/Line-Out.
Monaural Output to Internal Speaker or Telephony Subsystem Speakerphone.
Front Panel Headphone/Line-Out.
Rear Panel C/LFE Output.
Rear Panel C/LFE Output.
O
Switchable Microphone Bias. For use with Port B (Pins 21, 22).
O
Switchable Microphone Bias. For use with Port C (Pins 23, 24).
O
Switchable Microphone Bias. For use with Port E (Pins 14, 15).
O
CAUTION: DO NOT APPLY 3.3 V TO THIS PIN!
Filter connection for internal core voltage regulator.
This pin must be connected to filter caps: 10 μF, 1.0 μF, and 0.1 μF connected in
VREF_FLT
27
O
parallel between Pin 1 and DVSS (Pin 4).
Voltage Reference Filter. This pin must be connected to filter caps: 1.0 μF and 0.1μF
connected in parallel between Pin 27 and AVSS (Pins 26, 42).
The symbols used in this table are defined as: I = Input, O = Output, LI = Line level input, LO = Line level output, HP = Output capable of
driving headphone load, MIC = Input supports microphones with MIC bias and boost amplifier, SWAP = Outputs can swap L/R channels
(typically used to support C/LFE or shared C/LFE function).
Rev. A | Page 9 of 16 | April 2008
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