AD1865 Просмотр технического описания (PDF) - Analog Devices

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AD1865

Complete Dual 18-Bit 16 X 3 FS Audio DAC

Analog Devices 

AD1865–Analog Circuit Consideration

GROUNDING RECOMMENDATIONS

The AD1865 has three ground pins, two labeled AGND and

one labeled DGND. AGND, the analog ground pins, are the

“high quality” ground references for the device. To minimize

distortion and reduce crosstalk between channels, the analog

ground pins should be connected together only at the analog

common point in the system. As shown in Figure 6, the AGND

pins should not be connected at the chip.

–ANALOG

SUPPLY

VOUT

DIGITAL

SUPPLY

AD1865

1 –VS

+VS 24

2 TRIM TRIM 23

3 MSB MSB 22

4 IOUT

IOUT 21

5 AGND AGND 20

6 SJ

SJ 19

7 RF

8 VOUT

9 +VL

10 DR

RF 18

VOUT 17

NC 16

DL 15

11 LR

LL 14

12 CLK DGND 13

NC = NO CONNECT

ANALOG

SUPPLY

VOUT

DIGITAL

COMMON

Figure 6. Recommended Circuit Schematic

The digital ground pin returns ground current from the digital

logic portions of the AD1865 circuitry. This pin should be con-

nected to the digital common pin in the system. Other digital

logic chips should also be referred to that point. The analog and

digital grounds should be connected together at one point in the

system, preferably at the power supply.

POWER SUPPLIES AND DECOUPLING

The AD1865 has three power supply input pins. ± VS provides

the supply voltages which operate the analog portions of the

DAC including the voltage references, output amplifiers and

control amplifiers. The ± VS supplies are designed to operate

from ± 5 V supplies. Each supply should be decoupled to analog

common using a 0.1 µF capacitor in parallel with a 10 µF

capacitor. Good engineering practice suggests that the bypass

capacitors be placed as close as possible to the package pins.

This minimizes the parasitic inductive effects of printed circuit

board traces.

The +VL supply operates the digital portions of the chip includ-

ing the input shift registers and the input latching circuitry.

This supply should be bypassed to digital common using a

0.1 µF capacitor in parallel with a 10 µF capacitor. +VL oper-

ates with a +5 V supply. In order to assure proper operation of

the AD1865, –VS must be the most negative power supply volt-

age at all times.

Though separate positive power supply pins are provided for

the analog and digital portions of the AD1865, it is also possible

to use the AD1865 in systems featuring a single +5 V power

supply. In this case, both the +VS and +VL input pins should be

connected to the single +5 V power supply. This feature allows

reduction of the cost and complexity of the system power

supply.

As with most linear circuits, changes in the power supplies will

affect the output of the DAC. Analog Devices recommends that

well regulated power supplies with less than 1% ripple be incor-

porated into the design of an audio system.

DISTORTION PERFORMANCE AND TESTING

The THD+N figure of an audio DAC represents the amount of

undesirable signal produced during reconstruction and playback

of an audio waveform. The THD+N specification, therefore,

provides a direct method to classify and choose an audio DAC

for a desired level of performance. Figure 1 illustrates the typ-

ical THD+N performance of the AD1865 versus frequency. A

load impedance of at least 1.5 kΩ is recommended for best

THD+N performance.

Analog Devices tests and grades all AD1865s on the basis of

THD+N performance. During the distortion test, a high-speed

digital pattern generator transmits digital data to each channel

of the device under test. Eighteen-bit data is transmitted at

705.6 kHz (16 × FS). The test waveform is a 990.5 Hz sine wave

with 0 dB, –20 dB and –60 dB amplitudes. A 4096 point FFT

calculates total harmonic distortion + noise, signal-to-noise ratio,

D-Range and channel separation. No deglitchers or MSB trims

are used in the testing of the AD1865.

OPTIONAL MSB ADJUSTMENT

Use of optional adjust circuitry allows residual distortion error

to be eliminated. This distortion is especially important when

low amplitude signals are being reproduced. The MSB adjust

circuitry is shown in Figure 7. The trim potentiometer should

be adjusted to produce the lowest distortion using an input sig-

nal with a –60 dB amplitude.

200kΩ 100kΩ

470kΩ

AD1865

1 –VS

+VS 24

2 TRIM TRIM 23

470kΩ

3 MSB MSB 22

4 IOUT

IOUT 21

5 AGND AGND 20

6 SJ

SJ 19

7 RF

8 VOUT

9 +VL

10 DR

RF 18

VOUT 17

NC 16

DL 15

11 LR

LL 14

12 CLK DGND 13

100kΩ

200kΩ

NC = NO CONNECT

Figure 7. Optional THD+N Adjust Circuitry

–6–

REV. 0

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