AD1839A Просмотр технического описания (PDF) - Analog Devices
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AD1839A Datasheet PDF : 24 Pages
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AD1839A
Parameter
TDM256 MODE (Master, 48 kHz and 96 kHz)
tTBD
BCLK Delay
tFSD
FSTDM Delay
tTABDD
ASDATA Delay
tTDDS
DSDATA1 Setup
tTDDH
DSDATA1 Hold
TDM256 MODE (Slave, 48 kHz and 96 kHz)
fAB
BCLK Frequency
tTBCH
BCLK High
tTBCL
BCLK Low
tTFS
FSTDM Setup
tTFH
FSTDM Hold
tTBDD
ASDATA Delay
tTDDS
DSDATA1 Setup
tTDDH
DSDATA1 Hold
TDM512 MODE (Master, 48 kHz)
tTBD
BCLK Delay
tFSD
FSTDM Delay
tTABDD
ASDATA Delay
tTDDS
DSDATA1 Setup
tTDDH
DSDATA1 Hold
TDM512 MODE (Slave, 48 kHz)
fAB
BCLK Frequency
tTBCH
BCLK High
tTBCL
BCLK Low
tTFS
FSTDM Setup
tTFH
FSTDM Hold
tTBDD
ASDATA Delay
tTDDS
DSDATA1 Setup
tTDDH
DSDATA1 Hold
AUXILIARY INTERFACE (48 kHz and 96 kHz)
tAXDS
AAUXDATA Setup
tAXDH
AAUXDATA Hold
tDXD
DAUXDATA Delay
fABP
AUXBCLK Frequency
Slave Mode
tAXBH
AUXBCLK High
tAXBL
AUXBCLK Low
tAXLS
AUXLRCLK Setup
tAXLH
AUXLRCLK Hold
Master Mode
tAUXBCLK
AUXBCLK Delay
tAUXLRCLK
AUXLRCLK Delay
Min
15
15
256 × fS
17
17
10
10
15
15
15
15
512 × fS
17
17
10
10
15
15
15
10
10
10
64 × fS
15
15
10
10
20
15
Max Unit Comments
40
ns
From MCLK rising edge
5
ns
From BCLK rising edge
10
ns
From BCLK rising edge
ns
To BCLK falling edge
ns
From BCLK falling edge
ns
ns
ns
To BCLK falling edge
ns
From BCLK falling edge
15
ns
From BCLK rising edge
ns
To BCLK falling edge
ns
From BCLK falling edge
40
ns
From MCLK rising edge
5
ns
From BCLK rising edge
10
ns
From BCLK rising edge
ns
To BCLK falling edge
ns
From BCLK falling edge
ns
ns
ns
To BCLK falling edge
ns
From BCLK falling edge
ns
From BCLK rising edge
ns
To BCLK falling edge
From BCLK falling edge
ns
To AUXBCLK rising edge
ns
From AUXBCLK rising edge
ns
From AUXBCLK falling edge
ns
ns
ns
ns
To AUXBCLK rising edge
ns
From AUXBCLK rising edge
ns
From MCLK rising edge
ns
From AUXBCLK falling edge
MCLK
PD/RST
tMCLK
tMH
tML
tPDR
Figure 2. MCLK and PD/RST Timing
Rev. B | Page 6 of 24
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