AD1839A Просмотр технического описания (PDF) - Analog Devices
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AD1839A Datasheet PDF : 24 Pages
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TIMING SPECIFICATIONS
Table 2.
Parameter
MASTER CLOCK AND RESET
tMH
MCLK High
tML
MCLK Low
tPDR
PD/RST Low
SPI PORT
tCCH
tCCL
tCCP
tCDS
tCDH
tCLS
tCLH
tCOE
tCOD
tCOTS
DAC SERIAL PORT (48 kHz and 96 kHz)
CCLK High
CCLK Low
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
Normal Mode (Slave)
tDBH
tDBL
fDB
tDLS
tDLH
tDDS
tDDH
Packed 128/256 Modes (Slave)
tDBH
tDBL
fDB
tDLS
tDLH
tDDS
tDDH
ADC SERIAL PORT (48 kHz and 96 kHz)
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
Normal Mode (Master)
tABD
tALD
tABDD
Normal Mode (Slave)
tABH
tABL
fAB
tALS
tALH
tABDD
Packed 128/256 Mode (Master)
tPABD
tPALD
tPABDD
ABCLK Delay
ALRCLK Delay
ASDATA Delay
ABCLK High
ABCLK Low
ABCLK Frequency
ALRCLK Setup
ALRCLK Hold
ASDATA Delay
ABCLK Delay
LRCLK Delay
ASDATA Delay
AD1839A
Min
Max Unit Comments
15
ns
15
ns
20
ns
40
ns
40
ns
80
ns
10
ns
To CCLK rising edge
10
ns
From CCLK rising edge
10
ns
To CCLK rising edge
10
ns
From CCLK rising edge
15
ns
From CLATCH falling edge
20
ns
From CCLK falling edge
25
ns
From CLATCH rising edge
60
60
64 × fS
10
10
10
10
15
15
256 × fS
10
10
10
10
ns
ns
ns
To DBCLK rising edge
ns
From DBCLK rising edge
ns
To DBCLK rising edge
ns
From DBCLK rising edge
ns
ns
ns
To DBCLK rising edge
ns
From DBCLK rising edge
ns
To DBCLK rising edge
ns
From DBCLK rising edge
25
ns
From MCLK rising edge
5
ns
From ABCLK falling edge
10
ns
From ABCLK falling edge
60
ns
60
ns
64 × fS
5
ns
To ABCLK rising edge
15
ns
From ABCLK rising edge
15
ns
From ABCLK falling edge
40
ns
From MCLK rising edge
5
ns
From ABCLK falling edge
10
ns
From ABCLK falling edge
Rev. B | Page 5 of 24
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