AD13280BZ Просмотр технического описания (PDF) - Analog Devices
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AD13280BZ Datasheet PDF : 28 Pages
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AD13280
Parameter
I (DVCC) Current
ICC (Total) Supply Current per Channel
Power Dissipation (Total)
Power Supply Rejection Ratio (PSRR)
Temperature Test Level Min
Full
I
Full
I
Full
I
Full
V
AD13280AZ
Typ
Max
34
46
375
459
3.7
4.3
0.01
Unit
mA
mA
W
% FSR/% VS
1 All ac specifications tested by driving ENCODE and ENCODE differentially. Single-ended input: AMP-IN-x-1 = 1 V p-p, AMP-IN-x-2 = GND.
2 Gain tests are performed on the AMP-IN-x-1 input voltage range.
3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB.
4 For differential input: +IN = 1 V p-p and −IN = 1 V p-p (signals are 180 Ω out of phase). For single-ended input: +IN = 2 V p-p and –IN = GND.
5 Minimum and maximum conversion rates allow for variation in encode duty cycle of 50% ± 5%.
6 Analog input signal power at –1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 80 MSPS. SNR is
reported in dBFS, related back to converter full scale.
7 Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80 MSPS. SINAD is
reported in dBFS, related back to converter full scale.
8 Analog input signal at –1 dBFS; SFDR is the ratio of converter full scale to worst spur.
9 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third-order intermodulation product.
10 Channel-to-channel isolation tested with A channel grounded and a full-scale signal applied to B channel.
11 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF degrades performance.
12 Supply voltage recommended operating range. AVCC may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range
AVCC = 5.0 V to 5.25 V.
TIMING DIAGRAM
tA
N
AIN
N+1
N+2
ENCODE,
ENCODE
D[11:0]
tENC
N
tENCH
N+1
N–3
tENCL
N+2
tE_DR
N–2
N+3
N+3
N–1
N+4
N+4
tOD
N
DRY
Figure 2.
Rev. C | Page 6 of 28
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