ACT-7000SC-150F17C Просмотр технического описания (PDF) - Aeroflex Corporation
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ACT-7000SC-150F17C Datasheet PDF : 25 Pages
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Table 2 – Dual Issue Instruction Classes
Instruction
Cache
Dispatch
Unit
F Pipe IBus
M Pipe IBus
FP
F Pipe
FP
M Pipe
Integer Integer
F Pipe M Pipe
Figure 2 – Instruction Issue Paradigm
The figure illustrates that one F pipe instruction and
one M pipe instruction can be issued concurrently but
that two M pipe or two F pipe instructions cannot be
issued. Table 2 specifies more completely the
instructions within each class.
integer
load/store floating-point branch
add, sub, or, xor,
shift, etc.
lw, sw, ld, sd,
ldc1, sdc1,
mov, movc,
fmov, etc.
fadd, fsub, fmult, beq, bne,
fmadd, fdiv, fcmp, bCzT, bCzF, j,
fsqrt, etc.
etc.
The symmetric superscalar capability of the ACT
7000SC, in combination with its low latency integer
execution units and high-throughput fully pipelined
floating-point execution unit, provides unparalleled
price/performance in computational intensive
embedded applications.
Pipeline
The logical length of both the F and M pipelines is
five stages with state committing in the register write,
or W, pipe stage. The physical length of the
floating-point execution pipeline is actually seven
stages but this is completely transparent to the user.
Figure 3 shows instruction execution within the
ACT 7000SC when instructions are issuing
simultaneously down both pipelines. As illustrated in
the figure, up to ten instructions can be executing
simultaneously. This figure presents a somewhat
simplistic view of the processors operation however
since the out-of-order completion of loads, stores, and
I0 1l 2l 1R 2R 1A 2A 1D 2D 1W 2W
I1 1l 2l 1R 2R 1A 2A 1D 2D 1W 2W
I2
1l 2l 1R 2R 1A 2A 1D 2D 1W 2W
I3
1l 2l 1R 2R 1A 2A 1D 2D 1W 2W
I4
1l 2l 1R 2R 1A 2A 1D 2D 1W 2W
I5
1l 2l 1R 2R 1A 2A 1D 2D 1W 2W
I6
1l 2l 1R 2R 1A 2A 1D 2D 1W 2W
I7
1l 2l 1R 2R 1A 2A 1D 2D 1W 2W
I8
1l 2l 1R 2R 1A 2A 1D 2D 1W 2W
I9
1l 2l 1R 2R 1A 2A 1D 2D 1W 2W
one cycle
1I-1R: Instruction cache access
2I: Instruction virtual to physical address translation
2R: Register file read, Bypass calculation, Instruction decode, Branch address calculation
1A: Issue or slip decision, Branch decision
1A: Data virtual address calculation
1A-2A: Integer add, logical, shift
2A: Store Align
2A-2D: Data cache access and load align
1D: Data virtual to physical address translation
2W: Register file write
Figure 3 – Pipeline
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SCD7000SC REV B 7/30/01 Plainview NY (516) 694-6700
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