ACPL-38JT-500E Просмотр технического описания (PDF) - Avago Technologies
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производитель
ACPL-38JT-500E Datasheet PDF : 33 Pages
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1 GND1
0.1μF
2 VIN+
3 VIN
μC
4 VCC1
RF
5 RESET
6 FAULT
7 VLED+
8 VLED
VE 16
VLED2+ 15 0.1μF 0.1μF *
DESAT 14
VCC2 13
VEE 12
VC 11
0.1μF
*
CBLANK
100 Ω DDESAT
+ VF
RG
+
VOUT 10
VEE 9
RPULL-DOWN + *
+
VCE
Q1
Q2
Typical de-saturation protected gate drive circuit, non-inverting.
Description of Operation during Fault Condition
1. DESAT terminal monitors the IGBT VCE voltage through
DDESAT.
2. When the voltage on the DESAT terminal exceeds 7
volts, the IGBT gate voltage (VOUT) is slowly lowered.
3. FAULT output goes low, notifying the microcontroller
of the fault condition.
4. Microcontroller takes appropriate action.
Output Control
The outputs (VOUT and FAULT) of the ACPL-38JT are con-
trolled by the combination of VIN, UVLO and a detected
IGBT Desat condition. As indicated in the below table, the
ACPL-38JT can be configured as inverting or non-invert-
ing using the VIN+ or VIN- inputs respectively. When an
inverting configuration is desired, VIN+ must be held high
and VIN- toggled. When a non-inverting configuration
is desired, VIN- must be held low and VIN+ toggled. Once
UVLO is not active (VCC2 - VE > VUVLO), VOUT is allowed
to go high, and the DESAT (pin 14) detection feature of
the ACPL-38JT will be the primary source of IGBT protec-
tion. UVLO is needed to ensure DESAT is functional. Once
VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO-
< 12.4 V. Thus, the DESAT detection and UVLO features of
the ACPL-38JT work in conjunction to ensure constant
IGBT protection.
VIN+
VIN-
UVLO
(VCC2 - VE)
Desat
Pin 6
Condition (FAULT)
Detected Output
on Pin 14
VOUT
X
X
X
X
Low X
Active
X
X
Yes
X
X
X
Low
Low Low
X
Low
X
High X
X
X
Low
High Low
Not Active No
High High
3
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