ACE9030IW Просмотр технического описания (PDF) - Mitel Networks
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ACE9030IW Datasheet PDF : 39 Pages
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ACE9030
ELECTRICAL CHARACTERISTICS
These characteristics apply over these ranges of conditions (unless otherwise stated):
TAMB = – 40 °C to + 85 °C, VDD = + 3·6 to + 5·0 V, GND ref. = VSS
A.C. Characteristics
Parameter
CONTROL BUS
Clock rate CL input
Clock duty cycle CL input
tDS, input data set-up time
tDH, input data hold time
tCWL, tCWH, CL input pulse width (to bus logic)
tCL, delay time, clock to latch
tLW, latch pulse high time
tLH, delay time, latch to clock
tDSO, output data set-up time
tDHO, output data hold time
tZS, DATA line available to ACE9030
tZH, DATA line released by ACE9030
tCD, delay from received message to
transmitted response
Rise and Fall times, all digital inputs:
DIGITAL OUTPUTS
DOUT0 and 1 On time to VDD – 0·2 V
DOUT0 and 1 Off time to > 1 MΩ
DOUT5, 6 and 7 rise and fall times
DOUT8 rise and fall time
A to D CONVERTER
Lowest transition, 0000 0000 to 0000 0001
Highest transition, 1111 1110 to 1111 1111
ADC conversion time (20 cycles of CL)
Input scanning rate (CL ÷ 40)
Integral Non-linearity
Differential Non-linearity
Power supply sensitivity
CRYSTAL OSCILLATOR
Start-up time of crystal oscillator
Crystal effective series resistance (ESR)
Power dissipation in crystal
D to A CONVERTERS
Full scale output level, DAC1, DAC2 & DAC3
Zero scale output level, DAC1
Zero scale output level, DAC2 & DAC3
Integral Non-linearity
Differential Non-linearity
Output wideband and clock noise:
50 Hz to 1·1 MHz, flat integration
Power supply rejection ratio
Settling time to within 10% of end of step
(DAC3 with external 15 kΩ resistor)
Output load capacitance, DAC1 and DAC2
Output load capacitance, DAC3
Internal series resistor, DAC1 and DAC2
DAC3 output current, sink or source
Min.
40
80
80
400
440
230
220
80
80
80
80
4
0·07
3·35
–1
– 0·8
3·35
1·0
0·3
–1
– 0·5
30
7
1·0
Typ.
1008
50
0·15
3·45
20
25·2
50
3·45
15
Max.
60
600
1200
1200
4
50
100
100
10
10
0·23
3·55
+1
+ 0·8
3
5
25
150
3·55
1·2
0·5
+1
+ 0·5
3
6
100
30
40
Unit
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycles
of CL
ns
µs
µs
µs
µs
V
V
µs
kHz
LSB
LSB
LSB/0.3V
ms
Ω
µW
V
V
V
LSB
LSB
mVrms
dB
µs
nF
pF
kΩ
mA
Conditions
See Fig. 7
See Fig. 7
See Fig. 7
See Fig. 7
See Fig. 7
See Fig. 7
See Fig. 8
See Fig. 8
See Fig. 8
See Fig. 8
See Figs. 8 and 10
100 nF load and from
LATCHB rising edge
30 pF load and to D.C.
specification noise
Bandgap multiplier
correctly trimmed
CL = 1008 kHz
CL = 1008 kHz
0 to 10 kHz
Bandgap multiplier
trimmed to nominal
reference voltage
50 Hz to 25 kHz.
DAC1 and DAC2
10 pF load
To guarantee stability
7
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