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AAT4252A

Dual Slew Rate Controlled Load Switch

Analog Technology Inc 

AAT4252A

Dual Slew Rate Controlled Load Switch

First, the current duty cycle is calculated:

⎛ x ⎞ ⎛ 576μs ⎞

% Peak Duty Cycle = ⎝ 100⎠ = ⎝ 4.61ms⎠

% Peak Duty Cycle = 12.5%

The load current is 100mA for 87.5% of the 4.61ms

period and 2A for 12.5% of the period. Since the

Electrical Characteristics do not report RDS(MAX) for

4V operation, it must be approximated by consult-

ing the chart of RDS(ON) vs. VIN. The RDS reported

for 5V at 100mA and 2A can be scaled by the ratio

seen in the chart to derive the RDS for 4V VIN at

25°C : 155mΩ · 90mΩ/87mΩ = 160.3mΩ. De-rated

for temperature: 160.3mΩ · (1 + 0.002800 x (125°C

-25°C)) = 205mΩ. The power dissipation for a

100mA load is calculated as follows:

PD(MAX) = IOUT2 · RDS

PD(100mA) = (100mA)2 · 205mΩ

PD(100mA) = 2.05mW

PD(87.5%D/C) = %DC · PD(100mA)

PD(87.5%D/C) = 0.875 · 2.05mW

PD(87.5%D/C) = 1.8mW

The power dissipation for 100mA load at 87.5%

duty cycle is 1.97mW. Now the power dissipation

for the remaining 12.5% of the duty cycle at 2A is

calculated:

PD(MAX) = IOUT2 · RDS

PD(2A) = (2A)2 · 205mΩ

PD(2A) = 820.97mW

PD(12.5%D/C) = %DC · PD(2A)

PD(12.5%D/C) = 0.125 · 820.97mW

PD(12.5%D/C) = 102.6mW

The power dissipation for 2A load at 12.5% duty

cycle is 102.6mW. Finally, the two power figures

are summed to determine the total true power dis-

sipation under the varied load.

PD(total) = PD(100mA) + PD(2A)

PD(total) = 1.8mW + 102.6mW

PD(total) = 104.4mW

The maximum power dissipation for the AAT4252A

operating at an ambient temperature of 85°C is

250mW. The device in this example will have a

total power dissipation of 104.4mW. This is well

within the thermal limits for safe operation of the

device; in fact, at 85°C, the AAT4252A will handle

a 2A pulse for up to 30% duty cycle. At lower ambi-

ent temperatures, the duty cycle can be further

increased.

Printed Circuit Board Layout

Recommendations

For proper thermal management, and to take

advantage of the low RDS(ON) of the AAT4252A, a

few circuit board layout rules should be followed:

VIN and VOUT should be routed using wider than

normal traces, and GND should be connected to a

ground plane. For best performance, CIN and COUT

should be placed close to the package pins.

Evaluation Board Layout

The AAT4252A evaluation layout follows the print-

ed circuit board layout recommendations and can

be used for good applications layout. Refer to

Figures 1 and 2.

Note: Board layout shown is not to scale.

4252A.2007.06.1.0

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