A3949SLP-T Просмотр технического описания (PDF) - Allegro MicroSystems
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производитель
A3949SLP-T Datasheet PDF : 8 Pages
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PWM Control Timing Diagram
SLEEP
ENABLE
PHASE
MODE
VBB
OUTA
0V
VBB
OUTB
0V
A3949
DMOS Full-Bridge Motor Driver
IOUT
0A
A
VBB
1
2
3
4
5
6
7
8
9
VBB
OUTA
1
5
3
2
4
OUTB
OUTA
6
7
9
8
OUTB
A Charge pump and VREG power-up delay (approximately 200 us)
4
www.allegromicro.com
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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