A3949(2013) Просмотр технического описания (PDF) - Allegro MicroSystems
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A3949 Datasheet PDF : 7 Pages
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A3949
DMOS Full-Bridge Motor Driver
Functional Description
VREG. This supply voltage is used to operate the sink-
side DMOS outputs. VREG is internally monitored and in
the case of a fault condition, the outputs of the device are
disabled. The VREG pin should be decoupled with a 0.22 F
capacitor to ground.
Charge Pump. The charge pump is used to generate a
supply above VBB to drive the source-side DMOS gates. A
0.1 uF ceramic monolithic capacitor should be connected
between CP1 and CP2 for pumping purposes. A 0.1 uF
ceramic monolithic capacitor should be connected between
VCP and VBB to act as a reservoir to run the high side
DMOS devices. The VCP voltage is internally monitored,
and in the case of a fault condition, the outputs of the device
are disabled.
Shutdown. In the event of a fault due to excessive junction
temperature, or low voltage on VCP or VREG, the outputs of
the device are disabled until the fault condition is removed.
At power-up, the UVLO circuit disables the drivers.
Sleep Mode. Control input SLEEP is used to minimize
power consumption when the A3949 is not in use. This
disables much of the internal circuitry, including the low-side
gate supply and the charge pump. A logic low on this pin
puts the device into Sleep mode. A logic high allows normal
operation. After coming out of Sleep mode, the user should
wait 1 ms before applying PWM signals, to allow the charge
pump to stabilize.
Braking. The braking function is implemented by driv-
ing the device in slow decay mode via the MODE pin, and
applying an enable chop command. Because it is possible to
drive current in both directions through the DMOS switches,
this configuration effectively shorts out the motor-generated
BEMF, as long as the enable chop mode is asserted on the
ENABLE pin. The maximum current can be approximated
by VBEMF / RL. Care should be taken to insure that the maxi-
mum ratings of the device are not exceeded in worse case
braking situations of high speed and high inertial loads.
Control Logic Table
PHASE ENABLE MODE SLEEP OUTA OUTB
Function
1
1
X
1
H
L
Forward
0
1
X
1
L
H
Reverse
X
0
1
1
L
L
Brake (slow decay)
1
0
0
1
L
H
Fast decay SR*
0
0
0
1
H
L
Fast decay SR*
X
X
X
0
Hi-Z
Hi-Z
Sleep mode
* To prevent reversal of current during fast decay SR (synchronous rectification), the outputs
go to the high impedance state as the current approaches zero.
Allegro MicroSystems, LLC
5
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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