A3965 Просмотр технического описания (PDF) - Allegro MicroSystems

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A3965

DMOS Dual Full-Bridge PWM Motor Driver

Allegro MicroSystems 

3965 DMOS Dual Full Bridge

PWM Motor Driver

Functional Description

Sleep Mode. The input pin SLEEP is dedicated to put the

device into a minimum current draw mode. All circuits are

disabled including the VDD undervoltage monitor.

Shutdown. In the event of a fault due to excessive

junction temperature, or low voltage on VCP or VREG, the

outputs of the device are disabled until the fault condition is

removed. At power up, and in the event of low VDD, the

UVLO circuit disables the drivers

Current Regulation. Load current is regulated by a

fixed frequency PWM control circuit. When the outputs of

the DMOS H-bridge are turned on, current increases in the

motor winding until it reaches a value given by:

ITRIP = VREF/(6*RSENSE)

At the trip point, the sense comparator resets the source

enable latch, turning off the source. At this point, load

inductance causes the current to recirculate until the end

fixed frequency cycle. (see timing diagram)

VREF. The VREF voltage is divided down by 6 and

compared to the voltage across the sense resistor to set the

value of bridge current that will trip the PWM comparator.

The VREF input is a high impedance input and can be

connected to VDD, if desired, as well as via resistor divider.

Note: When connected to VDD, the VBB voltage must be 1.8V

greater than VDD to allow proper headroom for the buffer

output.

Fixed Frequency PWM. Selection of an external RC

sets the oscillator frequency as follows:

fOSC = 1/ ( 850ns + tBLANK+RTCT))

Blank Time. When a source driver turns on, a current

spike occurs due to the reverse recovery currents of the

clamp diodes and/or switching transients related to

distributed capacitance in the load. To prevent this current

spike from erroneously resetting the source enable latch, the

sense comparator is blanked. The blank duration is

determined by the time it takes to charge the external RC

.38*VDD volts with a 1mA current source.

tBLANK = CT*.38*VDD/ ( 1mA – ( .41*VDD/RT))

VREG. This supply voltage is used to run the sink side

DMOS outputs. VREG is internally monitored and in the

case of a fault condition, the outputs of the device are

disabled. The VREG pin should be decoupled with a 0.22

µF capacitor to ground.

Charge Pump. The Charge Pump is used to generate a

supply above VBB to drive the source side DMOS gates. A

0.22 uF ceramic monolithic capacitor should be connected

between CP1 and CP2 for pumping purposes. A 0.22 uF

ceramic monolithic capacitor should be connected between

VCP and VBB to act as a reservoir to run the high side

DMOS devices. The VCP Voltage is internally monitored and

in the case of a fault condition the outputs of the device are

disabled.

Thermal protection. Circuitry turns OFF all drivers

when the junction temperature reaches 165°C typically. It is

intended only to protect the device from failures due to

excessive junction temperatures and should not imply that

output short circuits are permitted. Thermal shutdown has a

hysteresis of approximately 15°C.

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