A3950 Просмотр технического описания (PDF) - Allegro MicroSystems

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A3950

DMOS Full-Bridge Motor Driver

Allegro MicroSystems 

Preliminary Data Sheet

Subject to Change without Notice

November 4, 2005

A3950

DMOS Full-Bridge Motor Driver

Applications Information

Power Dissipation. First order approximation of power

dissipation in the A3950 can be calculated by first examining

the power dissipation in the full-bridge during each of the

operation modes. The A3950 features synchronous rectifica-

tion, a feature that effectively shorts out the body diode by

turning on the low RDS(on) DMOS driver during the decay

cycle. This significantly reduces power dissipation in the

full-bridge. In order to prevent shoot-through, where both

source and sink driver are on at the same time, the A3950

implements a 500 ns typical crossover delay time. For this

period, the body diode in the decay current path conducts

the current until the DMOS driver turns on. This does affect

VBB

power dissipation and may need to be considered in high

current, high ambient temperature applications. In addition,

motor parameters and switching losses can add power dis-

sipation that could affect critical applications.

Drive Current. This current path is through source DMOS

driver, motor winding, and sink DMOS driver. Power dissi-

pation is I2R loses in one source and one sink DMOS driver,

as shown in the following equation:

PD = I 2 (RDS(on)Source + R ) DS(on)Sink

(1)

Fast Decay with Synchronous Rectification. This

decay mode is equivalent to a phase change where the oppo-

site drivers are switched on. When in fast decay, the motor

current is not allowed to go negative (direction change).

Instead, as the current approaches zero, the drivers turn off.

The power calculation is the same as the drive current calcu-

lation, equation 1:

1

3

2

1 Drive current

2 Fast decay with synchronous rectification (reverse)

3 Slow decay with synchronous rectification (brake)

Figure 1. Current Decay Patterns

Slow Decay SR (Brake Mode). In this decay mode, both

sink drivers turn on, allowing the current to circulate through

the sink drivers and the load. Power dissipation is I2R loses

in the two sink DMOS drivers:

PD = I 2 ( 2 × R ) DS(on)Sink

(2)

Layout. The printed circuit board should include a heavy

ground plane. For optimum electrical and thermal perfor-

mance, the exposed thermal pad of the device should be sol-

dered directly to an exposed copper area directly under the

device. The load supply pin, VBB, should be decoupled with

an electrolytic capacitor (typically 100 μF) in parallel with a

ceramic capacitor placed as close as possible to the device.

The ceramic capacitors between VCP and VBB, connected

to VREG, and between CP1 and CP2, should be as close to

the pins of the device as possible, in order to minimize lead

inductance.

A3950DS

Allegro MicroSystems, Inc.

7

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

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