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A3950SLP-T

DMOS Full-Bridge Motor Driver

Allegro MicroSystems 

Preliminary Data Sheet

Subject to Change without Notice

November 4, 2005

A3950

DMOS Full-Bridge Motor Driver

Functional Description

VREG. This supply voltage is used to run the sink-side

DMOS outputs. VREG is internally monitored and in the

case of a fault condition, the outputs of the device are dis-

abled. The VREG pin should be decoupled with a 0.22 μF

capacitor to ground.

Charge Pump. The charge pump is used to generate a

supply above VBB to drive the source-side DMOS gates. A

0.1 μF ceramic monolithic capacitor should be connected

between CP1 and CP2 for pumping purposes. A 0.1 μF

ceramic monolithic capacitor should be connected between

VCP and VBB to act as a reservoir to run the high-side

DMOS devices. The VCP voltage level is internally moni-

tored and, in the case of a fault condition, the outputs of the

device are disabled.

applying an enable chop command. Because it is possible to

drive current in both directions through the DMOS switches,

this configuration effectively shorts out the motor generated

BEMF as long as the ENABLE chop mode is asserted. The

maximum current can be approximated by VBEMF/RL. Care

should be taken to insure that the maximum ratings of the

device are not exceeded in worse case braking situations:

high speed and high-inertia loads.

Overcurrent Protection. The voltage on the output pins

relative to supply are monitored to ensure that the motor lead

is not shorted to supply or ground. If a short is detected, the

full-bridge outputs are turned off, flag NFAULT is driven

low, and a 1.2 ms fault timer is started.

Shutdown. In the event of a fault due to excessive junction

temperature, or low voltage on VCP or VREG, the outputs of

the device are disabled until the fault condition is removed.

At power-on the UVLO circuit disables the drivers.

Sleep Mode. Control input SLEEP is used to minimize

power consumption when the A3950 not in use. This disables

much of the internal circuitry, including the regulator and

charge pump. A logic low setting puts the device into Sleep

mode, and a logic high setting allows normal operation. After

coming out of Sleep mode, provide a 1 ms interval before

applying PWM signals, to to allow the charge pump to

stabilize.

After this 1.2 ms period, tOCP , the device will then be

allowed to follow the input commands and another turn-on is

attempted. If there is still a fault condition, the cycle repeats.

If, after tOCP expires, it is determined that the short condi-

tion is not present, the NFAULT pin is released and normal

operation resumes.

Diagnostic Output. The NFAULT pin signals a problem

with the chip via an open drain output. A motor fault, under-

voltage condition, or TJ > 160°C will drive the pin active

low. This output is not valid when SLEEP puts the device

into minimum power dissipation mode.

MODE. Control input MODE is used to toggle between

fast decay mode and slow decay mode. A logic high puts

the device in slow decay mode. Synchronus rectification is

always enabled.

Braking. The braking function is implemented by driving

the device in slow decay mode via the MODE setting and

TSD. Two die temperature monitors are integrated on the

chip. As die temperature increases towards the maximum, a

thermal warning signal will be triggered at 160°C. This fault

drives the NFAULT low, but does not disable the operation of

the chip. If the die temperature increases further, to approxi-

mately 175°C, the full-bridge outputs will be disabled until

the internal temperature falls below a hysteresis of 15°C.

A3950DS

Allegro MicroSystems, Inc.

6

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

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