A1359 Просмотр технического описания (PDF) - Allegro MicroSystems

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A1359

Factory-Programmed Dual Output Linear Hall Effect Sensor IC With Analog and Pulse Width Modulated Outputs

Allegro MicroSystems 

A1359

Factory-Programmed Dual Output Linear Hall Effect Sensor IC

With Analog and Pulse Width Modulated Outputs

Duty Cycle Jitter The duty cycle of the PWM output may vary

slightly over time despite the presence of a constant applied mag-

netic field and a constant Carrier Frequency, fPWM , for the PWM

signal. This phenomenon is known as jitter, JitterPWM (%) , and is

VCC

defined as:

VUVLOHI

VUVLOLO

JitterPWM

=

±

DB(max) –

2

DB(min)

(14)

tUVLO

where DB(max) and DB(min) are the maximum and minimum

duty cycles, measured in 1000 PWM clock periods, in a constant

applied magnetic field.

Undervoltage Lockout The A1359 features an undervolt-

age lockout function that ensures that the device will output a

valid signal when VCC is above a certain threshold, VUVLOHI ,

and remains valid until VCC falls below a lower threshold,

VUVLOLOW . The undervoltage lockout feature provides a hyster-

esis of operation to eliminate indeterminate output states.

The output of the A1359 is held low (GND) until VCC exceeds

VUVLOHI . When VCC exceeds VUVLOHI , the device powers-up

and the output provides a ratiometric output voltage proportional

to the input magnetic signal, and VCC . If VCC should drop back

down below VUVLOLOW for more than tuvlo after the device is

powered-up, the output would be pulled low. (See figure 5.)

PWM to Analog Output Mismatch When comparing the

PWM output to the analog output for channel mismatch, the

following equation is used to convert PWM (% D, duty cycle) to

voltage (V):

VPWMOUT = D(Q) + D(field) = VOUT(Q) × 20.0 %D / V

+ VOUT(B) × 21.0%D / V

(15)

where:

D(Q) is the quiescent PWM signal with no input field (B = 0 G),

and D(field) is the PWM signal in response to the input magnetic

field. In other words, the product of PWM sensitivity (%D/G)

and input magnetic field (G). (See figure 6.)

VPWMOUT

or VOUT

time

Figure 5. UVLO operation

+VPWMOUT (V)

Digital

Channel

3.75

3.25

VOUTERR=

±85 mV

1.75

VOUTERR=

±85 mV

1.25

VOUTERR=

±57.4 mV

1.25 1.75

3.25 3.75

+VOUT (V)

Analog Channel

Figure 6. Definition of PWM to Analog Output Mismatch, VOUTERR

Allegro MicroSystems, Inc.

9

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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