82574L Просмотр технического описания (PDF) - Intel
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82574L Datasheet PDF : 472 Pages
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Datasheet—82574 GbE Controller
7.1.5 Packet Split Receive Descriptor .............................................................. 128
7.1.6 Receive Descriptor Fetching ................................................................... 131
7.1.7 Receive Descriptor Write Back................................................................ 131
7.1.8 Receive Descriptor Queue Structure........................................................ 132
7.1.9 Receive Interrupts................................................................................ 134
7.1.10 Receive Packet Checksum Offloading ...................................................... 137
7.1.11 Multiple Receive Queues and Receive-Side Scaling (RSS)........................... 139
7.2 Packet Transmission ........................................................................................ 145
7.2.1 Transmit Functionality........................................................................... 145
7.2.2 Transmission Flow Using Simplified Legacy Descriptors.............................. 146
7.2.3 Transmission Process Flow Using Extended Descriptors.............................. 146
7.2.4 Transmit Descriptor Ring Structure ......................................................... 147
7.2.5 Multiple Transmit Queues ...................................................................... 149
7.2.6 Overview of On-Chip Transmit Modes...................................................... 149
7.2.7 Pipelined Tx Data Read Requests ............................................................ 150
7.2.8 Transmit Interrupts .............................................................................. 151
7.2.9 Transmit Data Storage .......................................................................... 151
7.2.10 Transmit Descriptor Formats.................................................................. 152
7.2.11 Extended Data Descriptor Format ........................................................... 160
7.3 TCP Segmentation ........................................................................................... 164
7.3.1 TCP Segmentation Performance Advantages ............................................ 164
7.3.2 Ethernet Packet Format......................................................................... 164
7.3.3 TCP Segmentation Data Descriptors........................................................ 165
7.3.4 TCP Segmentation Source Data .............................................................. 166
7.3.5 Hardware Performed Updating for Each Frame ......................................... 166
7.3.6 TCP Segmentation Use of Multiple Data Descriptors .................................. 167
7.4 Interrupts ...................................................................................................... 170
7.4.1 Legacy and MSI Interrupt Modes ............................................................ 170
7.4.2 MSI-X Mode......................................................................................... 170
7.4.3 Registers............................................................................................. 171
7.4.4 Interrupt Moderation ............................................................................ 173
7.4.5 Clearing Interrupt Causes...................................................................... 175
7.5 802.1q VLAN Support ...................................................................................... 176
7.5.1 802.1q VLAN Packet Format .................................................................. 176
7.5.2 Transmitting and Receiving 802.1q Packets ............................................. 177
7.5.3 802.1q VLAN Packet Filtering ................................................................. 177
7.6 LED's............................................................................................................. 178
7.7 Time SYNC (IEEE1588 and 802.1AS) ................................................................. 179
7.7.1 Overview ............................................................................................ 179
7.7.2 Flow and Hardware/Software Responsibilities ........................................... 180
7.7.3 Hardware Time Sync Elements ............................................................... 182
7.7.4 PTP Packet Structure ............................................................................ 185
8.0 System Manageability............................................................................................ 188
8.1 Scope ............................................................................................................ 188
8.2 Pass-Through (PT) Functionality ........................................................................ 188
8.3 Components of a Sideband Interface.................................................................. 189
8.4 SMBus Pass-Through Interface.......................................................................... 189
8.4.1 General............................................................................................... 190
8.4.2 Pass-Through Capabilities...................................................................... 190
8.4.3 Manageability Receive Filtering............................................................... 191
8.4.4 SMBus Transactions.............................................................................. 198
8.4.5 SMBus Notification Methods ................................................................... 202
8.5 Receive TCO Flow............................................................................................ 205
8.6 Transmit TCO Flow .......................................................................................... 205
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