82574L Просмотр технического описания (PDF) - Intel
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82574L Datasheet PDF : 472 Pages
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82574 GbE Controller—Datasheet
3.5 NC-SI...............................................................................................................58
3.5.1 Interface Specification .............................................................................59
3.5.2 Electrical Characteristics ..........................................................................59
4.0 Initialization ............................................................................................................60
4.1 Introduction ......................................................................................................60
4.2 Reset Operation.................................................................................................60
4.3 Power Up..........................................................................................................62
4.3.1 Power-Up Sequence ................................................................................62
4.3.2 Timing Diagram......................................................................................70
4.4 Global Reset (PE_RST_N, PCIe In-Band Reset) ......................................................71
4.4.1 Reset Sequence......................................................................................71
4.4.2 Timing Diagram......................................................................................72
4.5 Timing Parameters.............................................................................................74
4.5.1 Timing Requirements ..............................................................................74
4.5.2 MDIO and NVM Semaphore ......................................................................74
4.6 Software Initialization Sequence ..........................................................................75
4.6.1 Interrupts During Initialization..................................................................76
4.6.2 Global Reset and General Configuration .....................................................76
4.6.3 Link Setup Mechanisms and Control/Status Bit Summary .............................76
4.6.4 Initialization of Statistics..........................................................................78
4.6.5 Receive Initialization ...............................................................................78
4.6.6 Transmit Initialization..............................................................................79
5.0 Power Management and Delivery .............................................................................82
5.1 Assumptions .....................................................................................................82
5.2 Power Consumption ...........................................................................................82
5.3 Power Delivery ..................................................................................................83
5.3.1 The 1.9 V dc Rail ....................................................................................83
5.3.2 The 1.05 V dc Rail ..................................................................................83
5.4 Power Management............................................................................................83
5.4.1 82574 Power States ................................................................................83
5.4.2 Auxiliary Power Usage .............................................................................84
5.4.3 Power Limits by Certain Form Factors ........................................................85
5.4.4 Power States..........................................................................................85
5.4.5 Timing of Power-State Transitions .............................................................89
5.5 Wake Up ..........................................................................................................92
5.5.1 Advanced Power Management Wake Up .....................................................92
5.5.2 PCIe Power Management Wake Up ............................................................93
5.5.3 Wake-Up Packets....................................................................................93
6.0 Non-Volatile Memory (NVM) Map ........................................................................... 100
6.1 EEUPDATE ...................................................................................................... 100
6.2 Basic Configuration Table.................................................................................. 100
6.2.1 Hardware Accessed Words ..................................................................... 102
6.2.2 Software Accessed Words ...................................................................... 113
6.3 Manageability Configuration Words..................................................................... 114
6.3.1 SMBus APT Configuration Words ............................................................. 114
6.3.2 NC-SI Configuration Words .................................................................... 116
7.0 Inline Functions ..................................................................................................... 118
7.1 Packet Reception ............................................................................................. 118
7.1.1 Packet Address Filtering......................................................................... 118
7.1.2 Receive Data Storage ............................................................................ 119
7.1.3 Legacy Receive Descriptor Format........................................................... 119
7.1.4 Extended Rx Descriptor ......................................................................... 122
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