80931AA Просмотр технического описания (PDF) - Intel
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80931AA Datasheet PDF : 30 Pages
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8x931AA, 8x931HA USB PERIPHERAL CONTROLLER
5.2 DC Characteristics
Table 12. DC Characteristics at Operating Conditions
Symbol
Parameter
Min
Typical
(1)
Max
Units Test Conditions
VIL
Input Low Voltage
(except EA#)
–0.5
0.2 VCC – 0.1 V
VIL1
Input Low Voltage
0
(EA#)
0.2 VCC – 0.3 V
VIH
Input High Voltage
0.2 VCC + 0.9
(except XTAL1, RST)
VCC + 0.5
V
VIH1
Input High Voltage
(XTAL1, RST)
0.7 VCC
VCC + 0.5
V
VOL
VOL1
Output Low Voltage
(port 1, 2, 3)
(2)
Output Low Voltage
(port 0, ALE, PSEN#,
SOF#)
(2)
0.3
0.45
1.0
0.3
0.45
1.0
V IOL = 100 µA
IOL = 1.6 mA
IOL = 3.5 mA
V IOL = 200 µA
IOL = 3.2 mA
IOL = 7.0 mA
VOL2
VOH
Output Low Voltage
(LED 0, 1, 2, 3)
Output High Voltage
(port 1, 2, 3, ALE,
PSEN#, SOF#)
(3)
VCC – 0.3
VCC – 0.7
VCC – 1.5
2.0
V IOL = 6 mA
3.0
IOL = 22 mA
V IOH = –10 µA
IOH = –30 µA
IOH = –60 µA
VOH1
Output High Voltage
(port 0 in external
address space)
(3)
VCC – 0.3
VCC – 0.7
VCC – 1.5
V IOH = –200 µA
IOH = –3.2 mA
IOH = –7.0 mA
IIL
Logical 0 Input
Current
(port 1,2,3)
–50
µA VIN = 0.45 V
ILI
Input Leakage Current
(port 0)
±10
µA VIN = VIL or VIH
NOTE:
1. Typical values are obtained using VCC = 5.0V, TA = 25°C and are not guaranteed.
2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level
outputs of ALE and ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the
port 0 and port 2 pins when these pins change from 1 to 0. In applications where capacitive loading
exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify
ALE or other signals with a Schmitt trigger or CMOS-level input logic.
3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSEN to drop below the VCC
specification when the address lines are stabilizing.
ADVANCE INFORMATION
15
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