80931AA Просмотр технического описания (PDF) - Intel

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80931AA

UNIVERSAL SERIAL BUS PERIPHERAL CONTROLLERS

Intel 

8x931AA, 8x931HA USB PERIPHERAL CONTROLLER

4.0 SIGNALS

Table 8. Signal Description (Sheet 1 of 3)

Signal

Name

A15:8

AD7:0

ALE

AVCC

DM0, DP0

DM2, DP2

DM3, DP3

DM4, DP4

DM5, DP5

EA#

ECAP

FSSEL

Type

Description

Alternate

Function

O

I/O

O

PWR

I/O

I/O

I

I

Address Lines. Upper byte of external memory address.

Address/Data Lines. Lower byte of external memory address

multiplexed with data

Address Latch Enable. ALE signals the start of an external

bus cycle and indicates that valid address information is

available on lines A15:8 and AD7:0. An external latch can use

ALE to demultiplex the address from the address/data bus.

Analog VCC. A separate VCC input for the phase-locked loop

circuitry.

USB Port 0. Root port. Upstream port to the host PC. DP0 and

DM0 are the differential data plus and data minus signals of USB

port 0. These lines do not have internal pullup resistors. Provide

an external 1.5 KΩ pullup resistor at DP0 so the device indicates

to the host that it is a full-speed device; or provide an external

1.5 KΩ pullup resistor at DM0 so the device indicates to the host

that it is a low-speed device.

NOTE: DP0 low AND DM0 low signals an SE0 (USB reset),

causing the 8x931 to stay in reset.

USB External Downstream Ports 2, 3, 4,5. These pins are the

differential data plus and data minus lines for the four USB

external downstream ports. These lines do not have internal

pulldown resistors. Provide an external 15 KΩ pulldown resistor

at each of these pins. See “Design Considerations” on page

24.

External Access. Directs program memory accesses to on-

chip or off-chip code memory. For EA# strapped to ground, all

program memory accesses are off-chip. For EA# strapped to

VCC, program accesses on-chip ROM if the address is within the

range of the on-chip ROM; otherwise the access is off-chip. The

value of EA# is latched at reset. For devices without on-chip

ROM, EA# must be strapped to ground.

External Capacitor. Connect a 1 µF or larger capacitor

between this pin and VSS to ensure proper operation of the

differential line drivers. May be used to supply 3.0v to 3.6v for

1.5K pullup resistor connected to USB Port 0. See “Design

Considerations” on page 24.

Full Speed Select. Applies to the 8x931AA only. If this pin is

high, full speed USB data rate is selected (12Mbps). If pin is

low, low speed USB data rate is selected (1.5 Mbps). Refer to

Table 11.

P2.7:0/KS08:15

P0.7:0/KSI0:7

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ADVANCE INFORMATION

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