N8X931AA Просмотр технического описания (PDF) - Intel
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N8X931AA Datasheet PDF : 30 Pages
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8x931AA, 8x931HA USB PERIPHERAL CONTROLLER
5.1 Operating Frequencies
Table 10. 8x931HA Operating Frequency
PLLSEL
XTAL1
Frequency
(FOSC)
USB Rate
(1)
Internal
Frequency
(FCLK)
(2)
XTAL1
Clocks per
State
(TOSC/state)
(3)
Comments
0 (4)
–
–
–
–
–
1
12 MHz
12 Mbps
6 MHz (3)
2
PLL On
(Full Speed)
NOTES:
1. The sampling rate is 4 times the USB rate.
2. The internal frequency, FCLK = 1/TCLK, is the clock signal distributed to the CPU and the
on-chip peripherals,
3. Following device reset, the CPU and on-chip peripherals operate in low-clock mode
(FCLK = 3 MHz) until the LC bit in the PCON register is cleared. In low clock mode,
there are four TOSC periods per state. Low-clock mode does not affect the USB rate.
4. PLLSEL = 0 is used during factory test only.
.
Table 11. 8x931AA Operating Frequencies
PLLSEL FSSEL LC Bit
Pin
Pin
(1)
XTAL1
Frequency
(MHz)
USB Rate
(FS/LS)
(2)
Core
Frequency
FCLK
(Mhz)
Comment
0
0
0
6
LS
3
PLL Off
0
0
1
6
LS
3
PLL Off
1
0
0
12
LS
6
PLL Off
1
0
1
12
LS
3
PLL Off
1
1
0
12
FS
6
PLL On
1
1
1
12
FS
3
PLL On
NOTES:
1. Reset and power up routines set the LC bit in PCON to put the 8x931AA in low-clock mode (core
frequency = 3 MHz) for lower ICC prior to device enumeration. Following completion of device
enumeration, firmware should clear the LC bit to exit the low-clock mode. The user may switch the
core frequency back and forth at any time, as needed.
2. USB rates: Low speed = 1.5 Mbps; Full speed = 12 Mbps. The USB sample rate is 4X the USB rate.
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