PM8620-BIAP Просмотр технического описания (PDF) - PMC-Sierra
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PM8620-BIAP Datasheet PDF : 190 Pages
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NSE-20G™ Standard Product Data Sheet
Preliminary
List of Figures
Figure 1 An OC-48 T1/E1 ADM (Individually Drop/Add any T1/E1 in STS-48) ..............14
Figure 2 An OC-48 T1/E1 ADM (Drop/Add up to STS-48 at STS-1 Granularity)............14
Figure 3 Any-Service-Any-Port TDM Access Solution ....................................................15
Figure 4 Any-Service-Any-Port DS0-Granularity PHY Card ...........................................16
Figure 5 NSE-20G Block Diagram Showing TSBs..........................................................17
Figure 6 NSE-20G UBGA-480 Ball Diagram (Bottom-View)...........................................20
Figure 7 Analog Power Filter Circuit................................................................................42
Figure 8 Generic LVDS Link Block Diagram ...................................................................43
Figure 9 Character Alignment State Machine .................................................................50
Figure 10 Frame Alignment State Machine.....................................................................51
Figure 11 In-Band Signaling Channel Message Format .................................................55
Figure 12 In-Band Signaling Channel Header Format ....................................................55
Figure 13 Input Observation Cell (IN_CELL) ................................................................138
Figure 14 Output Cell (OUT_CELL) ..............................................................................139
Figure 15 Bidirectional Cell (IO_CELL) .........................................................................139
Figure 16 Layout of Output Enable and Bidirectional Cells...........................................139
Figure 17 Shutting down a link ......................................................................................141
Figure 18 “C1” Synchronization Control ........................................................................143
Figure 19 TEMUX-84™/SBS/NSE/SBS/AAL1GATOR-32™ system DS0
Switching with CAS.......................................................................................144
Figure 20 CAS Multiframe timing ..................................................................................145
Figure 21 Switch Timing DSOs with CAS .....................................................................145
Figure 22 TEMUX-84/SBS/NSE/SBS/FREEDM-336 system DS0 Switching no
CAS ............................................................................................................... 146
Figure 23 Switch Timing - DSOs without CAS ..............................................................147
Figure 24 Non DS0 Switch Timing ................................................................................148
Figure 25 Architecture of the RAM Input Interface........................................................150
Figure 26 C1 Position in the First Row..........................................................................155
Figure 27 Transport Overhead Affected by ILC ............................................................161
Figure 28 Example Graph .............................................................................................164
Figure 29 Time Space Time Switching in one NSE-20G and four Single-Ported
SBSs .............................................................................................................164
Figure 30 Example Graph .............................................................................................166
Figure 31 Example Problem..........................................................................................167
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
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Document ID: PMC-2000170, Issue 3
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