78Q2120C Просмотр технического описания (PDF) - Teridian Semiconductor Corporation
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78Q2120C Datasheet PDF : 35 Pages
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78Q2120C
10/100BASE-TX
Transceiver
PIN DESCRIPTION
LEGEND
TYPE DESCRIPTION
A Analog Pin
CIU TTL-level Input w/ Pull-up (5V compatible)
CID TTL-level Input w/ Pull-down
(5V compatible)
CIS TTL-level Input w/ Schmitt Trigger
(5V compatible)
CO CMOS Output
TYPE
CI
CIO
COZ
DESCRIPTION
TTL-level Input (5V compatible)
TTL-compatible Bi-directional Pin (5V compatible)
Tristate-able CMOS output
G Ground
S Supply
MII (MEDIA INDEPENDENT INTERFACE)
NAME
TX_CLK
TX_EN
TXD[3:0]
TX_ER
CRS
COL
RX_CLK
RX_DV
RXD[3:0]
PIN
27
28
32-29
26
34
33
24
23
19-22
TYPE
COZ
CI
CI
CI
COZ
COZ
COZ
COZ
COZ
DESCRIPTION
TRANSMIT CLOCK: TX_CLK is a continuous clock, which provides a timing
reference for the TX_EN, TX_ER and TXD[3:0] signals from the MAC. The
clock frequency is 25MHz in 100BASE-TX mode and 2.5MHz in 10BASE-T
mode. This pin is tristated in the isolate mode and the TXHIM mode.
TRANSMIT ENABLE: TX_EN is asserted by the MAC to indicate that valid
data for transmission is present on the TXD[3:0] pins.
TRANSMIT DATA: TXD[3:0] receives data from the MAC for transmission on
a nibble basis. This data is captured on the rising edge of TX_CLK when
TX_EN is high.
TRANSMIT ERROR: TX_ER is asserted high by the MAC to request that an
error code-group be transmitted when TX_EN is high. In PCS bypass mode
this pin becomes the MSB of the transmit 5-bit code group.
CARRIER SENSE: When the 78Q2120C is not in repeater mode, CRS is high
whenever a non-idle condition exists on either the transmitter or the receiver.
In repeater mode, CRS is only active when a non-idle condition exists on the
receiver. This pin is tristated in the isolate mode.
COLLISION: COL is asserted high when a collision has been detected on the
media. In 10BASE-T mode, COL is also used for the SQE test function. This
pin is tristated in the isolate mode. During half duplex operation, the rising
edge of COL will occasionally occur upon the rising edge of TX_CLK.
RECEIVE CLOCK: RX_CLK is a continuous clock, which provides a timing
reference to the MAC for the RX_DV, RX_ER and RXD[3:0] signals. The
clock frequency is 25MHz in 100BASE-TX mode, and 2.5MHz in 10BASE-T
mode. To reduce power consumption in 100BASE-TX mode, the 78Q2120C
provides an optional mode, enabled through MR16.0, in which RX_CLK is
held inactive (low) when no receive data is detected. This pin is tristated in
the isolate mode.
RECEIVE DATA VALID: RX_DV is asserted high to indicate that valid data is
present on the RXD[3:0] pins. In 100BASE-TX mode, it transitions high with
the first nibble of the preamble and is pulled low when the last data nibble has
been received. In 10BASE-T mode, it transitions high when the start-of-frame
delimiter (SFD) is detected. This pin is tristated in the isolate mode.
RECEIVE DATA: Received data is provided to the MAC via RXD[3:0]. These
pins are tristated in the isolate mode.
Page: 6 of 35
© 2009 Teridian Semiconductor Corporation
Rev 1.3
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