M37548G3-XXXFP Просмотр технического описания (PDF) - Renesas Electronics

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производитель

M37548G3-XXXFP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Renesas Electronics 

7548 Group

PERFORMANCE OVERVIEW

Table 1 Performance overview

Parameter

Number of basic instructions

Instruction execution time

Oscillation frequency

Memory sizes

ROM M37548G1

M37548G2

M37548G3

RAM M37548G1

M37548G2

M37548G3

I/O port

P00-P07 I/O

P10-P15 I/O

P20

Output

P21

I/O

Interrupts

Source

Timer

Output compare

Input capture

Serial interface

A/D converter

Watchdog timer

Power-on reset circuit

Low voltage detection circuit

Clock generating circuit

Function set ROM Function set ROM

area

ROM code protect

Power source

voltage

(at ceramic

resonator)

Double- at 8 MHz oscillation

speed at 2 MHz oscillation

mode at 1 MHz oscillation

High-

speed

mode

at 8 MHz oscillation

at 4 MHz oscillation

at 1 MHz oscillation

Power source

voltage

(at high-speed on-

chip oscillator)

Double- at 4 MHz oscillation

speed

mode

Power source

voltage

(at low-speed on-

chip oscillator)

Double- at 250 kHz oscillation

speed

mode

Power dissipation

Operating temperature range

Device structure

Package

Function

71

0.25 µs (Minimum instruction, oscillation frequency 8 MHz, double-speed mode)

8 MHz (Maximum)

2K bytes × 8 bits

4K bytes × 8 bits

6K bytes × 8 bits

192 bytes × 8 bits

256 bytes × 8 bits

256 bytes × 8 bits

1-bit × 8, LED direct drive ports

1-bit × 6

1-bit × 1

1-bit × 1

12 sources, 12 vectors

8-bit × 2, 16-bit × 1

3-channel

1 channel

8-bit × 1 (UART or clock synchronous)

10-bit resolution × 6 channel

16-bit × 1

Built-in

Built-in

Built-in (external ceramic resonator or quartz-crystal oscillator, external 32-kHz

quartz-crystal oscillator available) (built-in high/low-speed on-chip oscillator)

Function set ROM is assigned to address FFD816 to FFDA16.

Valid/invalid of low voltage detection circuit can be selected.

Oscillation mode can be selected.

Enable/disable of watchdog timer and STP instruction can be selected.

ROM code protect is assigned to address FFDB16.

Read/write the built-in QzROM by serial programmer is disabled by setting “00”

to ROM code protect.

4.5 to 5.5 V

2.4 to 5.5 V

2.2 to 5.5 V

4.0 to 5.5 V

2.4 to 5.5 V

1.8 to 5.5 V

4.0 to 5.5 V

1.8 to 5.5 V

30 mW

-20 to 85 °C

CMOS silicon gate

20-pin plastic molded SSOP (PLSP0020JB-A)

Rev.2.01 Oct 15, 2007 Page 4 of 81

REJ03B0210-0201

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