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74LVC240 Просмотр технического описания (PDF) - Philips Electronics

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74LVC240 Datasheet PDF : 16 Pages
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Philips Semiconductors
Octal buffer/line driver with 5 V tolerant
inputs/outputs; inverting (3-state)
Product specification
74LVC240A
FEATURES
5 V tolerant inputs/outputs, for interfacing with 5 V logic
Supply voltage range from 1.2 to 3.6 V
Complies with JEDEC standard no. 8-1A
CMOS low power consumption
Direct interface with TTL levels
High-impedance when VCC = 0 V.
DESCRIPTION
The 74LVC240A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V. These
features allow the use of these devices as translators in a
mixed 3.3 and 5 V environment.
The 74LVC240A is an octal non-inverting buffer/line driver
with 3-state outputs. The 3-state outputs are controlled by
the output enable inputs 1OE and 2OE. A HIGH on nOE
causes the outputs to assume a high-impedance
OFF-state. Schmitt trigger action at all inputs makes the
circuit highly tolerant for slower input rise and fall times.
The 74LVC240A is functionally identical to the
74LVC244A, which has non-inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 2.5 ns.
SYMBOL
tPHL/tPLH
CI
CPD
PARAMETER
propagation delay nAn to nYn
input capacitance
power dissipation capacitance per buffer
CONDITIONS
CL = 50 pF; VCC = 3.3 V
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
(CL × VCC2 × fo) = sum of outputs.
2. The condition is VI = GND to VCC.
TYPICAL
3.5
5.0
20
UNIT
ns
pF
pF
2002 Oct 02
2

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