74LV4053 Просмотр технического описания (PDF) - NXP Semiconductors.

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74LV4053

Triple single-pole double-throw analog switch

NXP Semiconductors. 

74LV4053

Triple single-pole double-throw analog switch

Rev. 04 — 10 August 2009

Product data sheet

1. General description

The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use

as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device

and is pin and function compatible with the 74HC4053 and 74HCT4053. Each switch has

a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common

input/output (nZ). All three switches share an enable input (E). A HIGH on E causes all

switches into the high-impedance OFF-state, independent of Sn.

VCC and GND are the supply voltage connections for the digital control inputs (Sn and E).

The VCC to GND range is 1 V to 6 V. The analog inputs/outputs (nY0, nY1 and nZ) can

swing between VCC as a positive limit and VEE as a negative limit. VCC − VEE may not

exceed 6 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND

(typically ground). VEE and VSS are the supply voltage connections for the switches.

2. Features

I Optimized for low-voltage applications: 1.0 V to 3.6 V

I Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

I Low ON resistance:

N 180 Ω (typical) at VCC − VEE = 2.0 V

N 100 Ω (typical) at VCC − VEE = 3.0 V

N 75 Ω (typical) at VCC − VEE = 4.5 V

I Logic level translation:

N To enable 3 V logic to communicate with ±3 V analog signals

I Typical ‘break before make’ built in

I ESD protection:

N HBM JESD22-A114-C exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

I Multiple package options

I Specified from −40 °C to +85 °C and from −40 °C to +125 °C

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