Philips Semiconductors
74LV4020
14-stage binary ripple counter
8. Functional description
8.1 Function table
Table 4: Function table [1]
Input
CP
MR
↑
L
↓
L
X
H
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
↑ = LOW-to-HIGH clock transition;
↓ = HIGH-to-LOW clock transition.
8.1.1 Timing diagram
Output
Q0, Q3 to Q13
no change
count
L
CP input
MR input
Q0
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384
001aad726
Fig 6. Timing diagram
74LV4020_1
Product data sheet
Rev. 01 — 29 November 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 20