74LCX573(2008) Просмотр технического описания (PDF) - Fairchild Semiconductor
Номер в каталоге
Компоненты Описание
производитель
74LCX573
(Rev.:2008)
(Rev.:2008)
Fairchild Semiconductor
74LCX573 Datasheet PDF : 14 Pages
| |||
Connection Diagrams
Pin Assignments for
SOIC, SOP, SSOP, TSSOP
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 O0
18 O1
17 O2
16 O3
15 O4
14 O5
13 O6
12 O7
11 LE
Pad Assignments for DQFN
OE VCC
1 20
D0 2
19 O0
D1 3
18 O1
D2 4
17 O2
D3 5
16 O3
D4 6
15 O4
D5 7
14 O5
D6 8
13 O6
D7 9
12 O7
10 11
GND LE
(Top View)
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs
Logic Symbol
D0 D1 D2 D3 D4 D5 D6 D7
LE
OE
O0 O1 O2 O3 O4 O5 O6 O7
Truth Table
Inputs
OE
LE
D
L
H
H
L
H
L
L
L
X
H
X
X
Outputs
On
H
L
O0
Z
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O0 = Previous O0 before HIGH-to-LOW transition of
Latch Enable
Functional Description
The LCX573 contains eight D-type latches with 3-STATE
output buffers. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this
condition the latches are transparent, i.e., a latch output
will change state each time its D input changes. When
LE is LOW the latches store the information that was
present on the D inputs a setup time preceding the
HIGH-to-LOW transition of LE. The 3-STATE buffers are
controlled by the Output Enable (OE) input. When OE is
LOW, the buffers are enabled. When OE is HIGH the
buffers are in the high impedance mode but this does not
interfere with entering new data into the latches.
Logic Diagram
D0
D1
D2
D3
D4
D5
D6
D7
D
D
D
D
D
D
D
D
Q
LE
Q
LE
Q
LE
Q
LE
Q
LE
Q
LE
Q
LE
Q
LE
LE
OE
O0
O1
O2
O3
O4
O5
O6
O7
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate
propagation delays.
©2006 Fairchild Semiconductor Corporation
74LCX573 Rev. 1.6.0
2
www.fairchildsemi.com
Share Link: