74F825SC(1999) Просмотр технического описания (PDF) - Fairchild Semiconductor
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производитель
74F825SC Datasheet PDF : 6 Pages
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Unit Loading/Fan Out
Pin Names
D0–D7
O0–O7
OE1, OE2, OE3
EN
CLR
CP
Description
Data Inputs
3-STATE Data Outputs
Output Enable Input
Clock Enable
Clear
Clock Input
U.L.
HIGH/LOW
1.0/1.0
150/40 (33.3)
1.0/1.0
1.0/1.0
1.0/1.0
1.0/2.0
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−1.2 mA
Functional Description
The 74F825 consists of eight D-type edge-triggered flip-
flops. This device has 3-STATE true outputs and is orga-
nized in broadside pinning. In addition to the clock and out-
put enable pins, the buffered clock (CP) and buffered
Output Enable (OE) are common to all flip-flops. The flip-
flops will store the state of their individual D inputs that
meet the setup and hold times requirements on the LOW-
to-HIGH CP transition. With the OE LOW the contents of
the flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Opera-
tion of the OE input does not affect the state of the flip-
flops. The 74F825 has Clear (CLR) and Clock Enable (EN)
pins.
When the CLR is LOW and the OE is LOW the outputs are
LOW. When CLR is HIGH, data can be entered into the flip-
flops. When EN is LOW, data on the inputs is transferred to
the outputs on the LOW-to-HIGH clock transition. When
the EN is HIGH the outputs do not change state, regard-
less of the data or clock input transitions.
Logic Diagram
Function Table
Inputs
Internal Output
OE CLR EN CP D Q
O
Function
H H L H X NC
Z Hold
H H L L X NC
Z Hold
H H H X X NC
Z Hold
L H H X X NC
NC Hold
H L X XX H
Z Clear
L
H
H
L
L
L
H
H
H
H
X XX
L
L
L
H
L
L
L
H
H
H
L
H
L
L Clear
Z Load
Z Load
L Data Available
H Data Available
L H L H X NC
NC No Change in Data
L H L L X NC
NC No Change in Data
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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