74F257ASJ Просмотр технического описания (PDF) - Fairchild Semiconductor
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74F257ASJ Datasheet PDF : 7 Pages
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Unit Loading/Fan Out
Pin Names
Description
S
OE
I0a–I0d
I1a–I1d
Za–Zd
Common Data Select Input
3-STATE Output Enable Input (Active LOW)
Data Inputs from Source 0
Data Inputs from Source 1
3-STATE Multiplexer Outputs
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
1.0/1.0
150/40 (33.3)
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−3 mA/24 mA (20 mA)
Truth Table
Output
Enable
Select
Input
OE
S
H
X
L
H
L
H
L
L
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Data
Inputs
I0
I1
X
X
X
L
X
H
L
X
H
X
Output
Z
Z
L
H
L
H
Functional Description
The 74F257A is a quad 2-input multiplexer with 3-STATE
outputs. It selects four bits of data from two sources under
control of a Common Data Select input. When the Select
input is LOW, the I0x inputs are selected and when Select
is HIGH, the I1x inputs are selected. The data on the
selected inputs appears at the outputs in true (non-
inverted) form. The device is the logic implementation of a
4-pole, 2-position switch where the position of the switch is
determined by the logic levels supplied to the Select input.
The logic equation for the outputs is shown below:
Zn = OE • (In• S + Ion • S)
When the Output Enable input (OE) is HIGH, the outputs
are forced to a high impedance OFF state. If the outputs
are tied together, all but one device must be in the high
impedance state to avoid high currents that would exceed
the maximum ratings. Designers should ensure the Output
Enable signals to 3-STATE devices whose outputs are tied
together are designed so there is no overlap.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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