74AHC74D Просмотр технического описания (PDF) - Philips Electronics

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производитель

74AHC74D

Dual D-type flip-flop with set and reset; positive-edge trigger

Philips Electronics 

Philips Semiconductors

Dual D-type flip-flop with set and reset;

positive-edge trigger

Product specification

74AHC74; 74AHCT74

SYMBOL PARAMETER

TEST CONDITIONS

WAVEFORMS CL

Tamb (°C)

25

−40 to +85 −40 to +125 UNIT

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

VCC = 4.5 to 5.5 V; note 2

tPHL/tPLH propagation delay see Figs 6 and 8 15 pF −

nCP to nQ, nQ

3.7 7.3 1.0 8.5 1.0 9.5 ns

propagation delay see Figs 7 and 8

nSD nRD to nQ, nQ

fmax

maximum clock

pulse frequency

− 3.7 7.7 1.0 9.0 1.0 10.0 ns

130 170 −

110 −

110 −

ns

tPHL/tPLH propagation delay see Figs 6 and 8 50 pF −

nCP to nQ, nQ

5.2 9.3 1.0 10.5 1.0 12.0 ns

propagation delay see Figs 7 and 8

nSD to nQ, nQ

tW

clock pulse width see Figs 6 and 8

HIGH or LOW

− 5.3 9.7 1.0 11.0 1.0 12.5 ns

5.0 −

−

5.0 −

5.0 −

ns

set or reset pulse see Figs 7 and 8

width LOW

5.0 −

−

5.0 −

5.0 −

ns

trem

removal time set or

reset

3.0 −

−

3.0 −

3.0 −

ns

tsu

set-up time

see Figs 6 and 8

nD to nCP

5.0 −

−

5.0 −

5.0 −

ns

th

hold time

nD to nCP

0.5 −

−

0.5 −

0.5 −

ns

fmax

maximum clock

pulse frequency

90 115 −

75 −

75 −

ns

Notes

1. Typical values at VCC = 3.3 V.

2. Typical values at VCC = 5.0 V.

1999 Sep 23

9

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