Philips Semiconductors
Dual D-type flip-flop with set and reset;
positive-edge trigger
AC WAVEFORMS
Product specification
74AHC74; 74AHCT74
handbook, full pagewidth
VI
nD INPUT
GND
VI
nCP INPUT
GND
VOH
nQ OUTPUT
VOL
VOH
nQ OUTPUT
VOL
VM(1)
th
t su
th
t su
1/fmax
VM(1)
tW
t PHL
VM(1)
t PLH
t PLH
VM(1)
t PHL
MNA422
FAMILY
AHC
AHCT
VI INPUT
REQUIREMENTS
GND to VCC
GND to 3.0 V
VM(1)
INPUT
50% VCC
1.5 V
VM(1)
OUTPUT
50% VCC
50% VCC
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.6 The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the
nCP to nD hold times, the output transition times and the maximum clock pulse frequency.
1999 Sep 23
11