GS8180Q18D-167(2002) Просмотр технического описания (PDF) - Giga Semiconductor

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GS8180Q18D-167
(Rev.:2002)

18Mb Σ2x2B2 SigmaQuad SRAM

Giga Semiconductor 

Preliminary

GS8180Q18/36D-200/167/133

Σ2x2B2 SigmaQuad SRAM DDR Write

The write port samples the status of the W pin at each rising edge of K and the Address Input pins on the following rising edge of K. A low on the

Write Enable-bar pin, W, begins a write cycle. The first of the data-in pairs associated with the write command is clocked in with the same rising

edge of K used to capture the write command. The second of the two data in transfers is captured on the rising edge of K along with the write

address. A high on W causes a write port deselect cycle.

Σ2x2B2 Double Data Rate SigmaQuad SRAM Write First

Dwg Rev. G

No Op

Write

Read

Write

Read

Write

Read

Write

K

/K

Address

XX

B

C

D

E

F

G

H

/R

/W

/BWx

DB0

DB1

DD0

DD1

DF0

DF1

DH0

DH1

D

C

/C

Q

QC0

QC1

CQ

/CQ

Rev: 2.00f 6/2002

7/29

© 2002, Giga Semiconductor, Inc.

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

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