GS8180Q18D-167(2002) Просмотр технического описания (PDF) - Giga Semiconductor
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GS8180Q18D-167 Datasheet PDF : 29 Pages
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Dwg Rev. G
K
/K
Address
/R1
/W1
/R2
/W2
D
Bank 1
D
Bank 2
C
/C
Q
Bank 1
Q
Bank 2
Q Bank 1 +
Q Bank 2
CQ
Bank 1
CQ
Bank 2
No Op
-
XX
Preliminary
GS8180Q18/36D-200/167/133
Σ2x2B2 SigmaQuad SRAM Depth Expansion
Read
Bank 2
Write
Bank 2
Read
Bank 1
Write
Bank 2
Read
Bank 1
Write
Bank 1
B
C
D
E
F
G
H
DG0
DG1
DC0
DC1
DE0
DE1
QD0
QB0
QB1
QB0
QB1
QD0
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaQuad SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to VSS via an external
resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line
impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between
150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and
temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may
move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary
Rev: 2.00f 6/2002
10/29
© 2002, Giga Semiconductor, Inc.
Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.
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