5962R9582401QQC Просмотр технического описания (PDF) - Intersil
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5962R9582401QQC Datasheet PDF : 16 Pages
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HS-80C85RH
TABLE 1. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
SYMBOL
(NOTE 1)
CONDITIONS
TEMPERATURE (oC)
MIN
Input Capacitance
CIN
VDD = Open, f = 1MHz
I/O Capacitance
CI/O VDD = Open, f = 1MHz
Output Capacitance
COUT VDD = Open, f = 1MHz
NOTE:
1. All measurements referenced to device ground.
TA = 25
-
TA = 25
-
TA = 25
-
MAX
12
13
12
UNITS
pF
pF
pF
TABLE 2. INTERRUPT PRIORITY, RESTART ADDRESS, AND SENSITIVITY
NAME
PRIORITY
ADDRESS BRANCHED TO (1) WHEN
INTERRUPT OCCURS
TYPE TRIGGER
TRAP
1
24H
Rising edge and high level until sampled.
RST 7.5
2
3CH
Rising edge (latched).
RST 6.5
3
34CH
High level until sampled.
RST 5.5
4
2CH
High level until sampled.
INTR
5
See Note 2
High level until sampled.
NOTES:
2. The processor pushes the PC on the stack before branching to the indicated address.
3. The address branched to depends on the instruction provided to the CPU when the interrupt is acknowledged.
TABLE 3. BUS TIMING SPECIFICATION AS A tCYC DEPENDENT
SYMBOL
HS-8OC85RH
SYMBOL
HS-8OC85RH
tAL
(1/2)T- 175
Minimum
tCC
(3/2 + N)T - 175
tLA
(1/2)T- 175
Minimum
tCL
(1/2)T - 190
tLL
(1/2)T-50
Minimum
tARY
(3/2)T - 500
tLCK
(1/2)T- 125
Minimum
tHACK
(1/2)T - 160
tLC
(1/2)T- 100
Minimum
tHABF
(1/2)T +125
tAD
(5/2 + N)T - 375
Maximum
tHABE
(1/2)T +125
tRD
(3/2 + N)T - 375
Maximum
tAC
(2/2)T - 200
tRAE
(1/2)T- 130
Minimum
t1
(1/2)T-210
tCA
(1/2)T - 100
Minimum
t2
(1/2)T- 150
tDW
(3/2 + N)T - 175
Minimum
tRV
(3/2)T - 200
tWD
(1/2)T-100
Minimum
tLDR
(4/2)T - 325
NOTE: N is equal to the total WAIT states T = tCYC.
Minimum
Minimum
Maximum
Minimum
Maximum
Maximum
Minimum
Minimum
Minimum
Minimum
Maximum
7
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