5962R9582401QQC(1996) Просмотр технического описания (PDF) - Intersil
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5962R9582401QQC Datasheet PDF : 19 Pages
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HS-80C85RH
Pin Description
SYMBOL
PIN
NUMBER TYPE
DESCRIPTION
A8 - A15
21-28
O
Address Bus: The most significant 8 bits of the memory address or the 8 bits of the I/O address,
3-stated during Hold and Halt modes and during RESET.
AD0-7
12-19
I/O Multiplexed Address/Data Bus: Lower 8 bits of the memory address (or I/O address) appear on
the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus
during the second and third clock cycles.
ALE
32
O
Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the
address to get latched into the on-chip latch of peripherals. The falling edge of ALE is set to guar-
antee setup and hold times for the address information. The falling edge of ALE can also be used
to strobe the status information. ALE is never 3-stated.
S0, S1, and
IO/M
31, 35,
& 36
O
Machine Cycle Status:
IO/M S1 S0 Status
0
0 1 Memory write
0
1 0 Memory write
1
0 1 I/O write
1
1 0 I/O read
0
1 1 Opcode fetch
1
1 1 Opcode fetch
1
1 1 Interrupt acknowledge
T
0 0 Halt
T
X X Hold
T
X X Reset
T = 3-State (high impedance)
X = Unspecified
S1 can be used as an advanced R/W status. IO/M, S0 and S1 become valid at the beginning of
a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used
to latch the state of these lines.
RD
34
O
Read Control: A low level on RD indicates the selected memory or I/O device is to be read and
that the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and dur-
ing RESET.
WR
33
O
Write Control: A low level on WR indicates the data on the Data Bus is to be written into the se-
lected memory or I/O location. Data is set up at the trailing edge of WR, 3-stated during Hold and
Halt modes and during RESET.
READY
35
I
Ready: If READY is high during a read or write cycle, it indicates that the memory or peripheral
is ready to send or receive data. If READY is low, the cpu will wait an integral number of clock
cycles for READY to go high before completing the read or write cycle. READY must conform to
specified setup and hold times.
HOLD
39
I
Hold: Indicates that another master is requesting the use of the address and data buses. The
cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion
of the current bus transfer. Internal processing can continue. The processor can regain the bus
only after the HOLD is removed. When the HOLD is acknowledged, the Address, Data Bus, RD,
WR, and IO/M lines are 3-stated.
HLDA
38
O
Hold Acknowledge: Indicates that the cpu has received the HOLD request and that it will relin-
quish the bus in the next clock cycle. HLDA goes low after the Hold request is removed. The cpu
takes the bus one half clock cycle after HLDA goes low.
Spec Number 518054
3
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