Power
Power
Power
Ground
Ground
Other
Supply
Ports
PLL
and
Clock
External
Address
Bus
or GPIO
External
Data
Bus
External
Bus
Control
VDD_IO
VDDA_OSC_PLL
VDDA_ADC
VSS
VSSA_ADC
OCR_DIS
VCAP1 - VCAP4
VPP1 & VPP2
CLKMODE
EXTAL
XTAL
CLKO
A0 - A5 (GPIOA8 - 13)
A6 - A7 (GPIOE2 - 3)
A8 - A15 (GPIOA0 - 7)
GPIOB0 - 3 (A16 - 19)
GPIOB4 (A20, prescaler_clock)
GPIOB5 (A21, SYS_CLK)
GPIOB6 (A22, SYS_CLK2)
GPIOB7 (A23, oscillator_clock)
D0 - D6 (GPIOF9 - 15)
D7 - D15 (GPIOF0 - 8)
RD
WR
PS / CS0 (GPIODF8)
DS / CS1 (GPIOFD9)
GPIOD0 - 5 (CS2 - 7)
7
1
1
1
1
1
6
1
1
56F8157
1
1
4
1
1
2
1
1
1
1
1
1
1
1
1
6
2
3
8
4
1
1
1
6
1
3
4
7
9
8
5
1
8
1
1
1
6
PHASEA0 (TA0, GPIOC4)
PHASEB0 (TA1, GPIOC5)
INDEX0 (TA2, GPIOC6)
HOME0 (TA3, GPIOC7)
SCLK0 (GPIOE4)
MOSI0 (GPIOE5)
MISO0 (GPIOE6)
SS0 (GPIOE7)
(SCLK1, GPIOC0)
(MOSI1, GPIOC1)
(MISO1, GPIOC2)
(SS1, GPIOC3)
(GPIOC8 - 10)
PWMB0 - 5
ISB0 - 2 (GPIOD10 - 12)
FAULTB0 - 3
ANA0 - 7
VREF
ANB0 - 7
Quadrature
Decoder 0
or Quad
Timer A
SPI0 or
GPIO
SPI 1 or
GPIO
GPIO
PWMB
ADCA
ADCB
SCI 0 or
GPIO
SCI 1
or GPIO
TXD0 (GPIOE0)
1
RXD0 (GPIOE1)
1
TXD1 (GPIOD6) 1
RXD1 (GPIOD7) 1
JTAG/
EOnCE
Port
TCK
1
TMS
1
TDI 1
TDO
1
TRST
1
* When the on-chip regulator is disabled, these
four pins become 2.5V VDD_CORE.
2
TC0 - 1 (GPIOE8 - 9)
4
(GPIOE10 - 13)
1
IRQA
IRQB
1
1
EXTBOOT
1
EMI_MODE
1
RESET
1
RSTO
Quad
Timer C or
GPIO
INTERRUPT/
PROGRAM
CONTROL
Figure 2-2 56F8157 Signals Identified by Functional Group1 (160-pin LQFP)
1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality.
56F8357 Technical Data, Rev. 15
18
Freescale Semiconductor
Preliminary