Architecture Block Diagram
To/From IPBus Bridge
CLKGEN
(OSC/PLL)
Timer A
4
Quadrature Decoder 0
4
Timer D
Timer B
4
Quadrature Decoder 1
Interrupt
Controller
Low Voltage Interrupt
POR & LVI
System POR
SIM
RESET
COP Reset
COP
FlexCAN
2
SPI 1
GPIO A
GPIO B
GPIO C
GPIO D
GPIO E
PWMA
PWMB
13
SYNC Output
13
SYNC Output
ch3i
ch2i
Timer C
2
ch3o
ch2o
GPIO F
4
SPI 0
2
SCI 0
2
SCI 1
NOT available on the 56F8157 device. IPBus
8
ADCB
ADCA
8
TEMP_SENSE
1
Note: ADC A and ADC B use the same volt-
age reference circuit with VREFH, VREFP,
VREFMID, VREFN, and VREFLO pins.
Figure 1-2 Peripheral Subsystem
56F8357 Technical Data, Rev. 15
Freescale Semiconductor
13
Preliminary