56F8013 Просмотр технического описания (PDF) - Freescale Semiconductor
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56F8013 Datasheet PDF : 126 Pages
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56F8013/56F8011 General Description
Note: Features in italics describe the 56F8011 device.
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 56F8013 device offers 16KB Program Flash
56F8011 device offers 12KB Program Flash
• 56F8013 device offers 4KB Unified Data/Program
RAM
56F8011 device offers 2KB Unified Data/Program
RAM
• One 6-channel PWM module
• Two 3-channel 12-bit ADCs
• One Serial Communication Interface (SCI) with LIN
slave functionality
• One Serial Peripheral Interface (SPI)
• One 16-bit Quad Timer
• One Inter-Integrated Circuit (I2C) Port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset and Low-Voltage Interrupt
Module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 26 GPIO lines
• 32-pin LQFP Package
7 PWM Outputs
3
AD0 ADC
or
GPIOC
3
AD1
PWM
or Timer Port
or GPIOA
Memory
Program Memory
8K x 16 Flash
6K x 16 Flash
Unified Data /
Program RAM
4KB
2KB
RESET
4
VCAP VDD
VSS
2
VDDA VSSA
JTAG/EOnCE
Port or
GPIOD
Digital Reg Analog Reg
16-Bit
56800E Core
Low-Voltage
Supervisor
Program Controller
and Hardware
Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
PAB
PDB
CDBR
CDBW
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
2
Timer or
GPIOB
IPBus Bridge (IPBB)
SPI or I2C
or Timer
or GPIOB
4
SCI
or I2C
or GPIOB
2
COP/
Watchdog
Interrupt
Controller
System P
Integration
O
R
Module
Clock
Generator*
O
S
C
*Includes On-Chip
Relaxation Oscillator
56F8013/56F8011 Block Diagram
56F8013/56F8011 Data Sheet, Rev. 12
4
Freescale Semiconductor
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