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AM29LV001BB-70FEB

1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

Advanced Micro Devices 

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8

Table 1. Am29LV001B Device Bus Operations ................................ 8

Requirements for Reading Array Data ..................................... 8

Writing Commands/Command Sequences .............................. 8

Program and Erase Operation Status ...................................... 9

Standby Mode .......................................................................... 9

Automatic Sleep Mode ............................................................. 9

RESET#: Hardware Reset Pin ................................................. 9

Output Disable Mode ................................................................ 9

Table 2. Am29LV001B Top Boot Sector Architecture .................... 10

Table 3. Am29LV001B Bottom Boot Sector Architecture................ 10

Autoselect Mode ..................................................................... 11

Table 4. Am29LV001B Autoselect Codes....................................... 11

Sector Protection/Unprotection ............................................... 11

Temporary Sector Unprotect .................................................. 11

Figure 1. In-System Sector Protect/Unprotect Algorithms ...............12

Figure 2. Temporary Sector Unprotect Operation ...........................13

Hardware Data Protection ...................................................... 13

Low VCC Write Inhibit .............................................................. 13

Write Pulse “Glitch” Protection ............................................... 13

Logical Inhibit .......................................................................... 13

Power-Up Write Inhibit ............................................................ 13

Command Definitions . . . . . . . . . . . . . . . . . . . . . 13

Reading Array Data ................................................................ 13

Reset Command ..................................................................... 13

Autoselect Command Sequence ............................................ 14

Byte Program Command Sequence ....................................... 14

Unlock Bypass Command Sequence ..................................... 14

Figure 3. Program Operation ..........................................................15

Chip Erase Command Sequence ........................................... 15

Sector Erase Command Sequence ........................................ 15

Erase Suspend/Erase Resume Commands ........................... 16

Figure 4. Erase Operation ...............................................................16

Command Definitions ............................................................. 17

Table 5. Am29LV001B Command Definitions ................................ 17

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 18

DQ7: Data# Polling ................................................................. 18

Figure 5. Data# Polling Algorithm ...................................................18

DQ6: Toggle Bit I .................................................................... 19

DQ2: Toggle Bit II ................................................................... 19

Reading Toggle Bits DQ6/DQ2 .............................................. 19

Figure 6. Toggle Bit Algorithm .........................................................20

DQ5: Exceeded Timing Limits ................................................ 20

DQ3: Sector Erase Timer ....................................................... 20

Table 6. Write Operation Status..................................................... 21

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 22

Figure 7. Maximum Negative Overshoot Waveform ...................... 22

Figure 8. Maximum Positive Overshoot Waveform ........................ 22

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 22

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 9. ICC1 Current vs. Time (Showing Active and Automatic

Sleep Currents) .............................................................................. 24

Figure 10. Typical ICC1 vs. Frequency ........................................... 24

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11. Test Setup ..................................................................... 25

Table 7. Test Specifications ........................................................... 25

Key to Switching Waveforms. . . . . . . . . . . . . . . . 25

Figure 12. Input Waveforms and Measurement Levels ................. 25

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26

Read Operations .................................................................... 26

Figure 13. Read Operations Timings ............................................. 26

Hardware Reset (RESET#) .................................................... 27

Figure 14. RESET# Timings .......................................................... 27

Erase/Program Operations ..................................................... 28

Figure 15. Program Operation Timings .......................................... 29

Figure 16. Chip/Sector Erase Operation Timings .......................... 30

Figure 17. Data# Polling Timings (During Embedded Algorithms) . 31

Figure 18. Toggle Bit Timings (During Embedded Algorithms) ...... 31

Figure 19. DQ2 vs. DQ6 ................................................................. 32

Temporary Sector Unprotect .................................................. 32

Figure 20. Temporary Sector Unprotect Timing Diagram .............. 32

Figure 21. In-System Sector Protect/Unprotect Timing Diagram ... 33

Alternate CE# Controlled Erase/Program Operations ............ 34

Figure 22. Alternate CE# Controlled Write Operation Timings ...... 35

Erase and Programming Performance . . . . . . . . 35

Latchup Characteristics . . . . . . . . . . . . . . . . . . . 36

TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 36

PLCC Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 36

Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 37

PL 032—32-Pin Plastic Leaded Chip Carrier ......................... 37

TS 032—32-Pin Standard Thin Small Outline Package ......... 38

TSR032—32-Pin Reverse Thin Small Outline Package ......... 39

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 40

Revision A (January 1998) ..................................................... 40

Revision A+1 (February 1998) ................................................ 40

Revision B (April 1998) ........................................................... 40

Revision C (April 1998) ........................................................... 40

Revision D (January 1999) ..................................................... 40

Revision E (November 17, 1999) ............................................ 40

Revision E+1 (November 13, 2000) ....................................... 40

Revision F (September 26, 2002) ........................................... 40

September 26, 2002

Am29LV001B

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