M48Z128 Просмотр технического описания (PDF) - STMicroelectronics
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M48Z128 Datasheet PDF : 17 Pages
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M48Z128
M48Z128Y
1 Mbit (128Kb x8) ZEROPOWER® SRAM
s INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
s CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
s 10 YEARS of DATA RETENTION in the
ABSENCE of POWER
s AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
s WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48Z128: 4.50V ≤ VPFD ≤ 4.75V
– M48Z128Y: 4.20V ≤ VPFD ≤ 4.50V
s BATTERY INTERNALLY ISOLATED UNTIL
POWER IS APPLIED
s PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 128K x 8 SRAMs
s SURFACE MOUNT CHIP SET PACKAGING
INCLUDES a 28-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)
s SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY
s SNAPHAT® HOUSING (BATTERY) IS
REPLACEABLE
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
NC
Not Connected Internally
June 2000
32
1
PMDIP32 (PM)
Module
SNAPHAT (SH)
Battery
TSO P32
(8 x 20mm)
SOH28
Surface Mount Chip Set Solution (CS)
Figure 1. Logic Diagram
VCC
17
A0-A16
8
DQ0-DQ7
W
M48Z128
M48Z128Y
E
G
VSS
AI01194
1/17
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