TQ6124-CM Просмотр технического описания (PDF) - TriQuint Semiconductor
Номер в каталоге
Компоненты Описание
производитель
TQ6124-CM Datasheet PDF : 9 Pages
| |||
TQ6124
AC Timing
The low-going transition of CLK latches the data.
Production SFDR testing is performed with the clock
transitioning in the center of the data eye. The timing of
the clock transition with respect to the data can
improve SFDR performance. Systems working to
optimize SFDR can 'tune' this phase relationship to
optimize the desired characteristic.
Figure 3. AC Timing Relationships
tDS
tDH
Data
Clock
Operating Notes
Current Source Control Loop
The full scale output voltage is set through the use of
an external op amp, as shown in Figure 4. Nominal full
scale output voltage can be achieved by using a voltage
source. With this, control voltages on the op amp of
around VAA+3V can be set. Adjusting the full scale
output voltage can be achieved by toggling the inputs
over full scale while adjusting the control voltage to
achieve the desired level.
Figure 4. Adjusting the Full-Scale Output Voltage
VAA
VAA
20 KΩ
620 Ω
+VIN VOUT
AD586
VAA
1KΩ
+
– MC34071
20 KΩ
1 KΩ
20 KΩ
VAA
1 KΩ
1 KΩ
LSB_TRIM
MID_TRIM
VREF
VSENSE
VREF Adjustment Range
The output full scale voltage range can be set through
the VREF input. Figure 5 shows the approximate
relationship between VREF and VFS.
Figure 5. Full-Scale Output Voltage vs. VREF
1.2
1.0
0.8
0.6
0.4
0.2
–1
0
1
2
3
4
Reference Voltage (vs VAA)
For additional information and latest specifications, see our website: www.triquint.com
5
Share Link: 