TQ6124 Просмотр технического описания (PDF) - TriQuint Semiconductor
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TQ6124 Datasheet PDF : 9 Pages
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TQ6124
Functional Description
The TQ6124 registers incoming bits in a master latch
array. The value of the four most-significant bits is
encoded into an n-of-15 thermometer code while the ten
low-order bits pass though an equalizing delay stage. All
25 bits are re-registered in a 25-wide slave latch array
which drives a set of 25 differential pair switches. These
switches steer the corresponding segment and bit
currents into the true (VO) and complementary (NVO)
outputs. This architecture minimizes glitch impulses by
eliminating large mid-scale current transitions.
The most-significant bits generate the segment
currents, which are of equal weight at 1/16 of the full-
scale output (IFS). The ten lower-order bits are divided
into two subgroups. The three intermediate bits steer
binary-weighted currents of magnitude IFS/32, IFS/64
and IFS/128 to the outputs. The seven least-significant
bits steer identical IFS/128 currents into a differential
R-2R ladder to generate effective bit currents of IFS/256
to IFS/16384. The DAC output is the sum of the
outputs of the segments and the low-order bits.
Clock and data inputs are ECL-compatible. The outputs
are designed to operate into a 50Ω load, with internal
reverse termination to ground being provided by the
R-2R network.
External compensation is utilized to minimize the effects
of device mismatch. An external op amp senses the sum
of the segment, the intermediate bit, and the LSB currents.
Figure 2. TQ6124 Currents
Segments 1 thru 15
VO
NVO
Q
NQ
To switches for D0 thru D9
ID9
ID8
ID7 dummy
1.25mA .625mA .3125mA .3125mA
ID6
.3125mA
dummy
.3125mA
2.5mA
(x8)
VREF
VSENSE
R SENSE
5.8KΩ
R SOURCE
1.2KΩ
RSENSE
5.8KΩ
RSOURCE
VAA
1.2KΩ
MID_trim
RSENSE
5.8KΩ
RSOURCE
1.2KΩ
LSB_trim
2
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