HFA3524IA96 Просмотр технического описания (PDF) - Intersil
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HFA3524IA96 Datasheet PDF : 15 Pages
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Block Diagram
HFA3524
VCC1 1
VP1 2
DO RF 3
4
GND
1X 4X
RF CHARGE PUMP
RF
LOCK
DETECT
PU
fOUT/
LOCK DETECT/
FASTLOCK
MULTIPLEXER
IF
LOCK
DETECT
1X 4X
IF CHARGE PUMP
PU
RF
FR 1
PD
PHASE
DETECTOR
FP 1
FR 2
IF
PHASE
FP 2 DETECTOR
PD
20 VCC2
19 VP2
18 DO IF
17
GND
5
fIN RF
fIN RF
6
-+
SWALLOW
CONTROL
32/33 OR 64/65
RF PRESCALER
PROGRAMMABLE
18-BIT (RF)
N-COUNTER
SWALLOW
CONTROL
PROGRAMMABLE
15-BIT (IF)
N-COUNTER
8/9 OR 16/17
IF PRESCALER
16
+-
15
fIN IF
fIN IF
1-BIT RF
PWDN
1-BIT P1
LATCH
(RF) 18-BIT N-LATCH
7
GND
5-BIT MODE LATCH
15-BIT R1 LATCH
8
OSCIN
9
GND
PROGRAMMABLE 15-BIT
(R1) REFERENCE COUNTER
PROGRAMMABLE 15-BIT
(R2) REFERENCE COUNTER
(IF) 15-BIT N-LATCH
1-BIT P2
LATCH
1-BIT IF
PWDN
14
GND
20-BIT SHIFT REGISTER
LATCH
DECODE
13
LE
2-BIT
CONTROL
LATCH
12
DATA
11
CLOCK
5-BIT MODE LATCH
15-BIT R2 LATCH
10
FOLD
NOTES:
1. VCC1 supplies power to the RF prescaler, N-counter and phase detector. VCC2 supplies power to the IF prescaler, N-counter and phase detector,
RF and IF R-counters along with the OSCIN buffer and all digital circuitry. VCC1 and VCC2 are separated by a diode and must be run at the
same voltage level.
2. VP1 and VP2 can be run independently as long as VP ≥ VCC.
4
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