EVAL-AD5324DBZ Просмотр технического описания (PDF) - Analog Devices
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производитель
EVAL-AD5324DBZ
Analog Devices
EVAL-AD5324DBZ Datasheet PDF : 24 Pages
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AD5305/AD5315/AD5325
Parameter2
LOGIC INPUTS (A0)5
Input Current
Input Low Voltage, VIL
Input High Voltage, VIH
Pin Capacitance
LOGIC INPUTS (SCL, SDA)5
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIN
Input Hysteresis, VHYST
Input Capacitance, CIN
Glitch Rejection
A Version1
B Version1
Min Typ
Max Min Typ
Max Unit
2.4
2.1
2.0
3
±1
0.8
0.6
0.5
2.4
2.1
2.0
3
±1
μA
0.8
V
0.6
V
0.5
V
V
V
V
pF
0.7
VDD
−0.3
0.05
VDD
8
VDD + 0.7
0.3
VDD
0.3 VDD −0.3
±1
0.05
VDD
8
50
VDD + V
0.3
0.3 VDD V
±1
μA
V
pF
50
ns
LOGIC OUTPUT (SDA)5
Output Low Voltage, VOL
0.4
0.4
V
0.6
0.6
V
Three-State Leakage Current
±1
±1
μA
Three-State Output
8
Capacitance
8
pF
POWER REQUIREMENTS
VDD
2.5
IDD (Normal Mode)7
5.5 2.5
5.5
V
VDD = 4.5 V to 5.5 V
600
900
600
900
μA
VDD = 2.5 V to 3.6 V
500
700
500
700
μA
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
0.2
1
0.2
1
μA
VDD = 2.5 V to 3.6 V
0.08 1
0.08 1
μA
Conditions/Comments
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
SMBus compatible at VDD < 3.6 V
SMBus compatible at VDD < 3.6 V
Input filtering suppresses noise spikes
of less than 50 ns
ISINK = 3 mA
ISINK = 6 mA
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
IDD = 4 μA (maximum) during
0 readback on SDA
IDD = 1.5 μA (maximum) during
0 readback on SDA
1 Temperature range (A, B version): −40°C to +105°C; typical at +25°C.
2 See the Terminology section.
3 DC specifications tested with the outputs unloaded.
4 Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981).
5 Guaranteed by design and characterization, not production tested.
6 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, VREF = VDD and offset plus gain error must be
positive.
7 IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
Rev. G | Page 4 of 24
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