VN16218L2 Просмотр технического описания (PDF) - Vaishali Semiconductor

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VN16218L2

2.5 Gigabit SERDES Transceiver

Vaishali Semiconductor  

VN16218

Advance Information

Equalizer

When EQEN is HIGH, the equalizer at the receiver is enabled, in order to correct for the frequency response

of the cable or other system components. The equalizer compensates for distortion introduced by the cable,

in order to maintain a low bit-error rate.

Input Latch

The transmitter accepts 20 bits wide single-ended parallel input T[0:19]. The TBC provided by the sender of

the transmit data is used as the transmit byte clock. The T[0:19] and TBC signals must be aligned as

shown in Figure 5. The T[0:19] data is latched on the rising edge of TBC.

Clock Recovery

When EWR is LOW, the VN16218 accepts differential high-speed inputs on the RX+ and RX- pins, extracts

the clock and retimes the data. The serial bit stream should be encoded in a Fibre Channel compatible

8B/10B, or equivalent format, in order to accomplish DC-balance and limited run length. Clock recovery

circuitry is self-contained and does not require external components. The baud rate of the data stream to be

recovered should be within 200 ppm of twenty times the TBC frequency. This allows oscillators at either

end of the link to be 125 MHz ± 100ppm.

Deserializer (Serial-to-Parallel Converter)

The re-timed serial bit stream is converted into two 10-bit parallel output characters. The VN16218 provides

a TTL recovered clock (RBC) at one-twentieth the serial baud rate. This is accomplished by dividing down

the high-speed clock that is phase locked to the serial data. The serial data is re-timed by the internal high-

speed clock and deserialized. Parallel data results, and is captured by the adjoining protocol logic on the

rising edge of RBC

Word Alignment

The VN16218 has 7-bit Fibre Channel comma character recognition, and data word alignment. Word

synchronization (with EN_CD HIGH), causes the VN16218 to constantly search the serial data for the

presence of the Fibre Channel ‘comma’ character. This pattern is ‘0011111XX’: the leading zero

corresponds to the first bit received. The comma sequence occurs only within special characters (K28.1,

K28.5 and K28.7) that are defined specifically for synchronization in Fibre Channel systems.

Improper alignment condition of the comma character is defined as;

1. The comma is not aligned within the 10 bit transmission character such that T0…T6 = ‘0011111’

2. The comma straddles the boundary between two 10-bit transmission characters.

When EN_CD is HIGH and an improperly aligned comma is encountered, the internal data is shifted so that

the comma character is aligned properly in R0:6, as shown in Table 2. The result is proper character and

word alignment. When an improperly aligned comma pattern causes changes in parallel data alignment,

some data that would have been presented at the parallel output port may be lost. However, the

synchronization character and subsequent data will be sent correctly and properly aligned. With EN_CD

LOW, the current alignment of the serial data is maintained indefinitely, regardless of data pattern.

A ‘comma’ character drives COM_DET HIGH to notify the user that realignment of the parallel data field

may have occurred. The COM_DET pulse occurs simultaneously with the ‘comma’ character and has a

duration equal to that of the data. The COM_DET pulse is timed so that it is captured by the adjoining

protocol logic, on the rising edge of RBC. Figures 3 and 4 show functional waveforms for synchronization.

Figure 3 illustrates the situation when a ‘comma’ character is detected, but no phase adjustment is

necessary. The position of the COM_DET pulse is shown in relation to the ‘comma’ character on R0:6.

Figure 4 illustrates the situation when K28.5 is detected, but is out- of-phase, and a change in the output

data alignment is required. It should be noted that up to three characters before the ‘comma’ character may

be corrupted by the realignment process.

2001-11-09

Page 5

MDSN-0003-00

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