VSC8162 Просмотр технического описания (PDF) - Vitesse Semiconductor

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VSC8162

2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC8162

2.488 Gbit/sec SONET/SDH

1:16 Demux with Clock Recovery

High Speed Clock Output

The high speed clock output is provided for test and measurement purposes. A termination method for the

high speed clock output is shown in Figure 5. In addition to the AC coupling method shown, the device may

also be DC coupled with a 50Ω resistor connected to VCC. By using these termination methods, a nominal volt-

age swing of 200mV - 300mV, single-ended peak-to-peak, can be expected.

In order to reduce noise on the board, the clock output can be disabled by using the CKOE pin. CKOE is a

normal ECL input, which, when left floating, will default to a low level (output disabled). In order to set the

CKOE pin to a logic high, it can be tied directly to VCC without the need for a resistor.

Figure 5: High-Speed Clock Output Termination

8162

CLK

VCC

270Ω

Zo = 50Ω

CLKN

270Ω

VCC

Zo = 50Ω

0.1 uF

0.1 uF

VTERM

50Ω

50Ω

VTERM

G52209-0, Rev. 2.0

9/14/98

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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