VSC8162 Просмотр технического описания (PDF) - Vitesse Semiconductor

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VSC8162

2.488 Gbit/sec SONET/SDH 1:16 Demux with Clock Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC8162

2.488 Gbit/sec SONET/SDH

1:16 Demux with Clock Recovery

Table 4: PLL Parameters

Parameters

Description

Min Typ Max Units

Conditions

RCd

RCf

∆fRC

tACQ

tset

tclr

tdensity

tjitter

ttolerance

REFCK Duty Cycle

REFCK Frequency

REFCK Frequency Tolerance

Acquisition time

Loss of Lock set time

Loss of Lock clear time

Maximum zero-timing-content

period

Jitter generationa

Jitter toleranceb

45

—

55

— 19.44 —

-100 — +100

—

—

20

2.3

—

100

125

—

250

— 1200 —

—

3.6

4.0

Exceeds mask in Figure 9

%

MHz

ppm

µs

µs

µs

—

—

—

With valid reference clock

From data interruption

From data restoration

UI For 0 BER

ps rms —

—

a. Measured at the HS clock output for jitter in the 12 kHz to 20 MHz band. Assume 1.2 ps rms input data jitter

b. Error-free operation guaranteed when electrical input signal is subject to jitter specified by mask in Figure 9.

Figure 12: VSC8162 Jitter Mask Specification

sinusoidal 30

input

15

jitter

slope = -20 dB/decade

amplitude

(UI p-p) 3.0

1.5

VSC8162 Mask

SONET/SDH Mask

0.30

0.15

10 600

6k

100k

frequency (Hz)

1000k

G52209-0, Rev. 2.0

9/14/98

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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